EEPW论坛

--****************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; --head files;
--****************************************************************
entity electron_watch is
port(reset,clk,clk0:in std_logic;
set_hour:in std_logic;
--set_min,set_sec:in std_logic;
sel:out std_logic_vector(2 downto 0);
number:out std_logic_vector(6 downto 0));
end entity;
--****************************************************************
architecture behave of electron_watch is
component divide_frequency
port(clk:in std_logic;
clk0:out std_logic);
end component;
component encoder
port(number:in std_logic_vector(3 downto 0);
seg7_number:buffer std_logic_vector(6 downto 0));
end component;
component count60
port(reset,clk:in std_logic;
carry_bit:out std_logic;
count0,count1:buffer std_logic_vector(3 downto 0));
end component;
component count24
port(reset,clk,set_hour:in std_logic;
count0,count1:buffer std_logic_vector(3 downto 0));
end component;
component select_led
port(clk:in std_logic;
sel:buffer std_logic_vector(2 downto 0));
end component;
signal carry_bit1,carry_bit2:std_logic;
signal clk1:std_logic;
signal sel_light:std_logic_vector(2 downto 0);
signal count_number1,count_number2,count_number3,count_number4,count_number5,count_number6:std_logic_vector(3 downto 0);
signal seg7_number1,seg7_number2,seg7_number3,seg7_number4,seg7_number5,seg7_number6:std_logic_vector(6 downto 0);
begin
clock:divide_frequency port map(clk0,clk1);
count1:count60 port map(reset,clk,carry_bit1,count_number1,count_number2);
count2:count60 port map(reset,carry_bit1,carry_bit2,count_number3,count_number4);
count3:count24 port map(reset,carry_bit2,set_hour,count_number5,count_number6);
sel_led:select_led port map(clk0,sel_light);
number0:encoder port map(count_number1,seg7_number1);
number1:encoder port map(count_number2,seg7_number2);
number2:encoder port map(count_number3,seg7_number3);
number4:encoder port map(count_number4,seg7_number4);
number5:encoder port map(count_number5,seg7_number5);
number6:encoder port map(count_number6,seg7_number6);
number<=seg7_number1 when sel_light="000" else
seg7_number2 when sel_light="001" else
seg7_number3 when sel_light="010" else
seg7_number4 when sel_light="011" else
seg7_number5 when sel_light="100" else
seg7_number6 when sel_light="101" else
"0000000";
sel<=sel_light;
end behave;
--******************************************************************