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 It is very encouraging to see several industry-wide efforts being made to achieve a common mean to integrate low-power-related design features into IC design flows. In the absence of such a standard, designers are left to their own ways when it comes to describing low-power concerns at various places within the design flow. As a result, most designers will shy away from the task and not risk having problems related to advanced low-power design techniques. Most designers tend to just stick with techniques that create the least problems and hence achieve limited results.
If one looks at today's design flow, there is currently no way to incorporate advanced low-power design intentions without having to create several instances of ad-hoc files describing special cells (e.g. isolation cells) and power-supply specifications (see figure 1). Without a single-file representation that could be integrated end to end in the design flow, designers would have to create keep managing unique sets of files to cover the needs of design, verification and implementation.

1. Today's IC design flow does not include power-aware features. To achieve power awareness, designers have to create several adjunct files.

Currently, several standardization efforts are at work, and it appears that the representative groups see value in arriving at a converged solution. One of these groups, representing the Common Power Format (CPF), will be used here as a model to illustrate the value of a standard.

Greater design efficiency
If one could include power-awareness from end to end in the design flow, it would greatly increase design efficiency. With a common format that design-tool vendors choose to integrate into their products, it would allow a single-file, power-aware description to be included early on and throughout the design flow (see figure 2). Any common format that does not include a single-file approach runs the risk of mitigated efficiency improvement.

2. Using a single-file approach, the Common Power Format integrates power awareness from end to end of the design chain.

To ensure buy-in from those who develop design, verification, and implementation tools, they should be involved in the creation and shaping of that common format. By necessity IC vendors should be included in the shaping of a common format since it is they who would benefit from such a standard and could provide early input to its development.

Not unprecedented
The idea for CPF and the way it would become part of the design flow is not unprecedented. The Synopsys SDC format is already being used in a similar way for timing-dependent designs.
Just as SDC and RTL combine to incorporate timing-aware elements and associated design constraints into a design, CPF and RTL could do the same for power-aware designs and power-related design constraints (see figure 3). CPF can describe virtually all necessary low-power design intents at the RTL design and verification phases, and can describe all constraints and conditions for creating actual design intents in the physical implementation phase. The important point here is that by using a common power format, it is possible to assure full data consistency and netlist equivalency in all design phases from RTL to GDS.

3. The common power format works analogously to RTL as SDC. When one is designing a timing-dependent IC, SDC integrates system interface, wire load, design constraints, timing constraints and other timing-aware considerations.

Let's take the simple logic design in Figure 4 as an example. The designer has decided to use two power-supply voltage levels Vdd and Vdd1, and power is turned off via a signal applied to PSMOD.

4. This RTL gate-level example illustrates how both timing-awareness and power-awareness can be included from end-to-end of the IC design flow.

In the timing design (see figure 5), RTL and SDC would provide clock and I/O pin interface information, the set up of some fixed logic, and the like.

Click here for figure 5

5. Clock and I/O pin interfaces are included in the design along with some fixed logic. These features are added due to SDC's timing-aware descriptions.

In the low-power design phase, where RTL and CPF are combined, the specifications provide the power-supply net and common ground, level shifting between the two power-supply areas, and a power-switch circuit. These are the kinds of design features that would ordinarily have required additional information files in tool-specific formats, to be provided for design, then again for verification, and again for implementation. With the single CPF file, however, the tools automatically take account of these power-aware specifications to also make synthesis, simulation and verification power aware.

Click here for figure 6

6. CPF has added power supply nets, level shifting, isolation elements and a power-supply control switch. Ordinarily, such features would have had to be described by adjunct files, such as those in figure 1.

Tool vendors still have much work to do
Having a common format for power-aware design description is meaningless unless it becomes pervasive. That means it will require design tools that can read and write that format. In addition, its use has to be extensive and include the following:

• A multiple power-supply library that efficiently describes the timing and power information for multiple voltages,
• Tools that support equivalence verification and automatically insert power supply isolation elements and level shifters,
• Timing verification for power-supply control circuits,
• Timing verification for paths that cross multiple power supply areas,
• Layout design tools that can optimize via batch-verification multiple operation modes and timing situations, and
• Technology that automates the testing of power-supply control circuits.

The success of a common power format will depend in large part on the buy-in of many EDA vendors. It is not sufficient for only one vendor to support it. It would need support from most major EDA companies which would then drive the momentum towards general EDA acceptance.

Going forward
Including basic low-power design features, such as multiple power supplies, may enhance design efficiency. At the same time, the miniaturization trend will lead to more power-consumption increases. Several power-aware architectural breakthroughs using more advanced low-power techniques, such as dynamic voltage control using dynamic voltage and frequency scaling, and adaptive body bias, will further enable low-power design. These too will have to be included in and supported by a common power format for design, verification and implementation tools.

The industry has been making significant efforts to improve low-power design. In order to help increase IC design efficiency, there are two kinds of extensions for low power format, a single file approach without RTL modification, and an extension of RTL languages. The single-file approach without RTL modification has significant benefit so that a designer does not need to change existing RTL libraries and also RTL design methodologies. On the other hand, the RTL language extension is straightforward and does not require multiple files, but is less flexible, since it may not be enough to describe all low-power design intents for a particular implementation. The combination with a single-file common format and extended RTL language will be the ultimate goal. In both cases, all EDA vendors need to cooperate to establish them, and all tools need to understand the same format.

As a single-file common power format, CPF may provide a basis for all related standardization works. And by including and supporting advanced low-power techniques, CPF can help insure that the more efficient IC designs are also producing more power-efficient IC end products.