以下是递归型卷积编码的移位存储器部分,编译室总出现“trans_1 has multiple soueces”不知道是为什么,希望高手帮忙看看逻辑上有什么错误,谢谢!
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY juanji_1 IS
PORT(clk:IN STD_LOGIC;
a,se:IN STD_LOGIC;
Uk:OUT STD_LOGIC);
END juanji_1;
ARCHITECTURE shifter OF juanji_1 IS
SIGNAL trans_1:STD_LOGIC_VECTOR(0 TO 7);
SIGNAL b0,seo:STD_LOGIC;
COMPONENT dff
PORT(d,clk:IN STD_LOGIC;
q:OUT STD_LOGIC);
END COMPONENT;
COMPONENT mux2
PORT(d0,d1,sel:IN STD_LOGIC;
q:OUT STD_LOGIC);
END COMPONENT;
BEGIN
j1:FOR i IN 0 TO 6 GENERATE
j11:IF(i=0)GENERATE
muxx:mux2 PORT MAP(a,b0,se,seo);
dffx:dff PORT MAP(seo,clk,trans_1(i+1));
END GENERATE;
j12:IF(i+1=7)GENERATE
dffx:dff PORT MAP(trans_1(i),clk,Uk);
END GENERATE;
j13:IF(i=0) AND ((i+1)/=7)GENERATE
dffx:dff PORT MAP(trans_1(i),clk,trans_1(i+1));
END GENERATE;
END GENERATE;
PROCESS(clk)
BEGIN
IF(se='1')THEN
seo<=a;
trans_1(0)<=seo;
ELSE
b0<=trans_1(3) XOR trans_1(7);
seo<=b0;
trans_1(0)<=seo;
END IF;
IF(clk'EVENT AND clk='1')THEN
FOR i IN 0 TO 6 LOOP
trans_1(i+1)<=trans_1(i);
END LOOP;
END IF;
Uk<=trans_1(7);
END PROCESS;
END shifter;