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附件图中，如何消除latch_signal的竞争冒险(不可引入新的时钟或其它信号，还有将clk_base两次not的方法我也试过了，没有效果)

我的程序如下

USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counting_controller IS
PORT(clk_base:IN STD_LOGIC;
     latch_signal,gate_signal,cleared_signal:OUT STD_LOGIC);
END counting_controller;

ARCHITECTURE countingcontroller OF counting_controller IS
  SIGNAL latchsignal,gatesignal,clearedsignal:STD_LOGIC;
BEGIN
  latch_signal<=latchsignal;
  gate_signal<=gatesignal;
  cleared_signal<=clearedsignal;

  latchsignal<=clk_base and  (NOT gatesignal);

  clearedsignal<=(NOT clk_base) AND (not latchsignal) AND (not gatesignal);
  clkbase<=NOT (not clk_base);
process(clk_base)
    BEGIN
      IF(clk_base'EVENT AND clk_base='1')THEN
        gatesignal<=NOT gatesignal;

      END IF;

  END process;

END countingcontroller;