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Sr. Digital ASIC design engineer

Job Description

The position is to lead one project in the field of communication system on the whole ASIC design flow from RTL to GDSII, and FPGA-based prototyping test, then to deliver quality design results. Work independently in different stages of the ASIC design flow. Cooperate closely with system/algorithm team and analog team.

Requirement
1. Master degree with 2+ years of experience of digital ASIC development in communication system physical layer.
2. Familiar with digital ASIC front-end design and related tools, including micro-architecture design, RTL design and coding, simulation.
3. Familiar with logic synthesis, DFT, static timing analysis, ATPG, and power analysis.
4. Experience in FPGA-based prototyping test is a plus.
5. Good understanding of wireless communication system and digital signal processing theory.
6. Has ability of independent debugging and self-learning.
7. Experience of audio or video SOC product development is a plus.

Email:aitbj@126.com
MSN:aitbj@126.com