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【应用手册】Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design
This application note describes Single-Port Triple-Speed Ethernet and On-Board PHY
Chip reference designs that demonstrate Ethernet operations of the Altera®
Triple-Speed Ethernet MegaCore® functions with on-board Marvell 88E1111 PHY
chips. The reference designs provide flexible test and demonstration platforms on
which you can control, test, and monitor the Ethernet operations using system
loopbacks.
One reference design runs in the Arria® II GX FPGA development board and
integrates one instance of the media access controller (MAC) function. The Triple-
Speed Ethernet IP core connects to the on-board PHY chip through Reduced Gigabit
Media Independent Interface (RGMII).
The other reference design runs in the Stratix® IV GX FPGA development board and
integrates one instance of the MAC with physical coding sublayer (PCS) and physical
medium attachment (PMA) functions. The Triple-Speed Ethernet IP core connects to
the on-board PHY chip through Serial Gigabit Media Independent Interface (SGMII)
mode.an647.pdf