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The TRI primitive is a tri-state buffer with an input, output, and output enable signal. If the output enable input to the TRI buffer is high, the output is driven by the Input.

The output enable defaults to VCC.

If the output enable of a TRI buffer is connected to VCC or a logic function that minimizes to true, a TRI buffer may be converted into a SOFT buffer during logic synthesis. For supported device(Cyclone, Cyclone II, Stratix, and Stratix GX) families, some configurations of TRI primitives and other logic are automatically converted into OPNDRN buffers.

When you use a TRI buffer, you must observe the following rules in addition to the rules listed in Primitive/Port Interconnections:

• A TRI buffer may drive only one BIDIR pin. You must use a BIDIR pin if feedback is included after the TRI buffer.

• If a TRI buffer feeds logic, it must also feed a BIDIR pin unless it is part of a tri-state bus. If it feeds a BIDIR pin it may not feed any other outputs.

• The TRI primitive cannot be used in Verilog as TRI is a reserved word in the Verilog language. Use the ALT_OUTBUF_TRI primitive instead, or use the equivalent behavioral Verilog, for example:
  assign out = oe ? in : 1'bZ;
  
  但目前还不知道如何进行管脚约束？