3-3按键除抖
module key(CLK,RESET,KEY,LED);
input CLK;
input RESET;
input KEY;
output LED;
reg LED;
reg [19:0] delay_cnt;
wire kscan;
wire klow;
reg ksamp;
reg ksampr;
reg krst;
reg krstr;
//edge detect
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
ksamp<=1'b1;
else
ksamp<=KEY;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
ksampr<=1'b1;
else
ksampr<=ksamp;
end
assign kscan=ksampr&(~ksamp);
//delay 20ms
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt<=20'h0;
else if(kscan)
delay_cnt<=20'h0;
else
delay_cnt<=delay_cnt+1'b1;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
krst<=1'b1;
else if(delay_cnt==20'hfffff)
krst<=KEY;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
krstr<=1'b1;
else
krstr<=krst;
end
assign klow=krstr&(~krst);
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
LED<=1'b1;
else if(klow)
LED<=~LED;
else
LED<=LED;
end
endmodule
http://player.youku.com/player.php/sid/XNTI4MjYwNzAw/v.swf
3-4 按键除抖+数码管
module key(CLK,RESET,KEY,SEG,DIG);
input CLK;
input RESET;
input KEY;
output [7:0] SEG;
output [7:0] DIG;
reg LED;
reg [19:0] delay_cnt;
wire kscan;
wire klow;
reg ksamp;
reg ksampr;
reg krst;
reg krstr;
reg [7:0] SEG;
wire [7:0] DIG;
reg [3:0] dat;
//edge detect
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
ksamp<=1'b1;
else
ksamp<=KEY;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
ksampr<=1'b1;
else
ksampr<=ksamp;
end
assign kscan=ksampr&(~ksamp);
//delay 20ms
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt<=20'h0;
else if(kscan)
delay_cnt<=20'h0;
else
delay_cnt<=delay_cnt+1'b1;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
krst<=1'b1;
else if(delay_cnt==20'hfffff)
krst<=KEY;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
krstr<=1'b1;
else
krstr<=krst;
end
assign klow=krstr&(~krst);
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
dat<=1'b1;
else if(klow)
dat<=dat+1'b1;
else
dat<=dat;
end
always@(dat)
begin
case(dat)
4'h0: SEG = 8'hc0;
4'h1: SEG = 8'hf9;
4'h2: SEG = 8'ha4;
4'h3: SEG = 8'hb0;
4'h4: SEG = 8'h99;
4'h5: SEG = 8'h92;
4'h6: SEG = 8'h82;
4'h7: SEG = 8'hf8;
4'h8: SEG = 8'h80;
4'h9: SEG = 8'h90;
4'ha: SEG = 8'h88;
4'hb: SEG = 8'h83;
4'hc: SEG = 8'hc6;
4'hd: SEG = 8'ha1;
4'he: SEG = 8'h86;
4'hf: SEG = 8'h8e;
endcase
end
assign DIG=8'b11111110;
endmodule
http://player.youku.com/player.php/sid/XNTI4MjY1NDY0/v.swf
4.蜂鸣器
教程蜂鸣器例题1module fmq(CLK,RESET,BEEP);
// I/O
input CLK;
input RESET;
output BEEP;
reg BEEP;
reg [24:0] div;
reg [14:0] delay_cnt;
wire [14:0] delay_end;
parameter clk_div0=56817;//50000000/2*440-1
parameter clk_div1=28408;//50000000/4*440-1
assign delay_end=div[24]?clk_div0:clk_div1;
蜂鸣器作业一
变化不大
module fmq(CLK,RESET,BEEP);
// I/O
input CLK;
input RESET;
output BEEP;
reg BEEP;
reg [24:0] div;
reg [14:0] delay_cnt;
wire [14:0] delay_end;
parameter clk_div0=28408;//50000000/4*440-1
parameter clk_div1=14204;//50000000/8*440-1
assign delay_end=div[24]?clk_div0:clk_div1;
//div
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
div<=25'd0;//???25??????0
else
div<=div+1'b1;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt<=delay_end;
else if(delay_cnt==15'd0)
begin
BEEP<=~BEEP;
delay_cnt<=delay_end;
end
else
delay_cnt<=delay_cnt-1'b1;
end
endmodule
蜂鸣器例题2
一个按键对应一个音,中音区需要按着第八个键不放,再继续
module fmq(CLK,RESET,KEY,BEEP);
// I/O
input CLK;
input RESET;
input [7:0] KEY;
output BEEP;
reg BEEP;
reg [15:0] delay_cnt;
reg [15:0] delay_end;
//delay
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt<=16'd0;//???25??????0
else if((delay_cnt==delay_end)&(!(delay_end==16'hffff)))
begin
delay_cnt<=16'd0;
BEEP=~BEEP;
end
else
delay_cnt=delay_cnt+1'b1;
end
always@(KEY)
begin
case(KEY)
8'b11111110:delay_end=16'd47774;//m1
8'b11111101:delay_end=16'd42568;//m2
8'b11111011:delay_end=16'd37919;//m3
8'b11110111:delay_end=16'd35791;//m4
8'b11101111:delay_end=16'd31888;//m5
8'b11011111:delay_end=16'd28409;//m6
8'b10111111:delay_end=16'd25309;//m7
8'b01111110:delay_end=16'd23912;//h1
8'b01111101:delay_end=16'd21282;//h2
8'b01111011:delay_end=16'd18961;//h3
8'b01110111:delay_end=16'd17897;//h4
8'b01101111:delay_end=16'd15944;//h5
8'b01011111:delay_end=16'd14205;//h6
8'b00111111:delay_end=16'd12655;//h7
default:delay_end=16'd0;
endcase
end
endmodule
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