Warning: (vsim-3473) Component instance "I1 : inv" is not bound.
# Time: 0 ns Iteration: 0 Instance: /decode File: F:/eryi/eryi.vhd
# ** Warning: (vsim-3473) Component instance "I2 : inv" is not bound.
# Time: 0 ns Iteration: 0 Instance: /decode File: F:/eryi/eryi.vhd
# ** Warning: (vsim-3473) Component instance "A1 : and3" is not bound.
# Time: 0 ns Iteration: 0 Instance: /decode File: F:/eryi/eryi.vhd
# ** Warning: (vsim-3473) Component instance "A2 : and3" is not bound.
# Time: 0 ns Iteration: 0 Instance: /decode File: F:/eryi/eryi.vhd
# ** Warning: (vsim-3473) Component instance "A3 : and3" is not bound.
# Time: 0 ns Iteration: 0 Instance: /decode File: F:/eryi/eryi.vhd
# ** Warning: (vsim-3473) Component instance "A4 : and3" is not bound.
# Time: 0 ns Iteration: 0 Instance: /decode File: F:/eryi/eryi.vhd
我把顶层文件还有各个子模块都放在了一个工程下，对顶层文件仿真时就会出现这个问题，添加信号以后没有输出。求指导！谢谢！
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