一个是锁定DDR2引脚后综合到map时出现错误:
LIT:600 - IOBUFDS symbol
"processor_i/DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dqs[0].u_iob_dqs/gen_dqs_iob_ddr2.u_iobuf_dqs" (output
signal=processor_i/DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy
_if_0/u_phy_io_0/gen_dqs[0].u_iob_dqs/dqs_ibuf) does not have IOSTANDARD
specified. Map is unable to generate a default IOSTANDARD for IOBUFDS, one
has to be explicitly provided
还有是 使用别人搭好软核自己编程后进行到最后program FPGA时出现错误 提示
ELF file :
E:/xilinx_project/without_cam_fin/SDK/empty_application_0/Debug/empty_applicatio
n_0.elf
ERROR:EDK:3165 - elfcheck failed!
The following sections did not fit into Processor BRAM memory:
Section .jcr (0x9000072C - 0x9000072F)
Section .eh_frame (0x90000728 - 0x9000072B)
Section .data (0x90000618 - 0x90000727)
Section .rodata (0x90000610 - 0x90000615)
Section .dtors (0x90000608 - 0x9000060F)
Section .ctors (0x90000600 - 0x90000607)
Section .fini (0x900005E4 - 0x900005FF)
Section .init (0x900005A8 - 0x900005E3)
Section .text (0x90000000 - 0x900005A7)
Try using the linker script generation tools to generate an ELF that maps
correctly to your hardware design.
Programming the FPGA failed due to errors from elfcheck