EEPW论坛

这是红外篇的作业，开发板的两个数码管是有译码的。

这是实验现象：http://v.youku.com/v_show/id_XNzI5MTg1NzQ4.html

/***************************************************

* Company:        EEPW
* Engineer:       Superdian  
* 
* Create Date:    2014/6/20 
* Design Name:    hongwai2
* Module Name:    hongwai2  
* Project Name:   hongwai2
* Target Devices: EP3C5E144
* Tool versions: 
* Description: 
****************************************************/
module hongwai2(sys_clk,sys_rstn,ir,sm_seg,sm_bit,SHUMAGUAN1,SHUMAGUAN2);         

//输入定义  

input          sys_clk;
input          sys_rstn;
input          ir;

//输出定义

output  [7:0]  sm_seg;
output         sm_bit;
output  [3:0] SHUMAGUAN1;//开发板的对应数码管有有译码
output  [3:0] SHUMAGUAN2;//开发板的对应数码管有有译码

//寄存器定义              

reg     [7:0]  sm_seg;
reg     [9:0]  delay_cnt;
reg            div_clk;
reg            ir_reg0;
reg            ir_reg1;
reg     [8:0]  ir_cnt;
reg     [4:0]  rec_cnt;
reg     [3:0]  SHUAMGUAN1;
reg     [3:0]  SHUAMGUAN2;
reg     [7:0]  key_code;
reg     [3:0]  SHUMAGUAN1;
reg     [3:0]  SHUMAGUAN2;
reg     [31:0] data;

wire           sm_bit;

wire           ir_posedge;
wire   ir_negedge;
wire           t_9ms;
wire           t_4ms;
wire           low;
wire           highe;

assign         t_9ms=((9'd217 < ir_cnt)& (ir_cnt < 9'd297)); 

assign         t_4ms=((9'd88 < ir_cnt) & (ir_cnt < 9'd168));
assign         low=((9'd22 < ir_cnt) & (ir_cnt < 9'd42));
assign         high=((9'd54 < ir_cnt) & (ir_cnt < 9'd74));
assign         ir_posedge=(~ir_reg1)&ir_reg0;
assign         ir_negedge=ir_reg1&(~ir_reg0);
assign         sm_bit = 1'b0;


//状态机定义
reg     [7:0]  ir_state;
parameter
  idle          =8'h01,
  waite_posedge =8'h02,
  check_9ms     =8'h04,
  waite_negedge =8'h08,
  check_4ms     =8'h10,
  rec_code      =8'h20;






//时钟分频
always@(posedge sys_clk ,negedge sys_rstn)
begin
     if(!sys_rstn)
        begin
        delay_cnt<=10'd0;
        div_clk<=1'b0;

end

     else if(delay_cnt==11'd350)//开发板上的晶振为20MHZ，做了相应修改。

begin
       delay_cnt<=10'd0;
       div_clk<=~div_clk;
end
    else
begin
        delay_cnt<=delay_cnt+1'b1 ;
        div_clk<=div_clk;
end
end




//捕捉红外信号的上下沿
always@(posedge div_clk ,negedge sys_rstn)
begin
if(!sys_rstn)
begin
ir_reg0<=1'b0;
ir_reg1<=1'b0;
end
else
begin
ir_reg0<=ir;
ir_reg1<=ir_reg0;
end
end




//状态机部分
always@(posedge div_clk , negedge sys_rstn)
begin
if(!sys_rstn)
begin
ir_cnt<=9'd0;
rec_cnt<=5'd0;
key_code<=8'h0;
data<=32'h0;
ir_state<=idle;
end
else
begin
case(ir_state)
idle:
begin
if(~ir_reg0)
begin
ir_state<=waite_posedge;
ir_cnt<=9'd0;
rec_cnt<=5'd0;
end
else
ir_state<=idle;
end
waite_posedge:
begin
ir_cnt<=ir_cnt+1'b1;
if(ir_posedge)
ir_state<=check_9ms;
else
ir_state<=waite_posedge;
end
check_9ms:
begin
if(t_9ms)
begin
ir_state<=waite_negedge;
ir_cnt<=9'd0;
end
else
ir_state<=idle;
end
waite_negedge:
begin
ir_cnt<=ir_cnt+1'b1;
if(ir_negedge)
ir_state<=check_4ms;
else
ir_state<=waite_negedge;
end
check_4ms:
begin
if(t_4ms)
begin
ir_state<=rec_code;
ir_cnt<=16'd0;
end
else
ir_state<=idle;
end
rec_code:
begin
ir_cnt<=ir_cnt+1'b1;
if(ir_negedge)
begin
rec_cnt<=rec_cnt+1'b1;
ir_cnt<=9'd0;
if(low)
data[rec_cnt] <= 1'b0;
else if(high)
data[rec_cnt] <= 1'b1;
else
ir_state<=idle;
if(rec_cnt==5'd31)
begin
ir_state<=idle;
key_code<=data[23:16];
   SHUMAGUAN1<=data[31:28];
   SHUMAGUAN2<=data[27:24];
   
end
end
else
ir_state<=rec_code;
end
default:
ir_state<=idle;
endcase
end
end

//开发板最下方的数码管需要译码，共阴的。

always @(key_code)
begin
case (key_code)  
8'h16 : sm_seg = 8'h3F;   // "0"
8'h0c : sm_seg = 8'h06;   // "1"
8'h18 : sm_seg = 8'h5B;   // "2"
8'h5e : sm_seg = 8'h4F;   // "3"
8'h08 : sm_seg = 8'h66;   // "4"
8'h1c : sm_seg = 8'h6D;   // "5"
8'h5a : sm_seg = 8'h7D;   // "6"
8'h42 : sm_seg = 8'h07;   // "7"
8'h52 : sm_seg = 8'h7F;   // "8"
8'h4a : sm_seg = 8'h6F;   // "9"
default:
   sm_seg = 8'h3F;   // "0"
endcase 
    end
       
endmodule