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//Software Ver: Quartus II 9.1sp2
//EDA Tool: ModelSim ALTERA6.5b

module clkdiv_prj(
clk,rst_n,
tp1,tp2,tp3,tp4
);

input clk; //clock signal, 50MHz
input rst_n;//reset signal, low voltage enable

output tp1,tp2,tp3,tp4;

reg tp1_r,tp2_r,tp3_r,tp4_r;

//----------------------------------------------------------
//-----使用Gate Level Simulation: tp1,tp2感觉代码一直在执行(见下图),
//-----always @(敏感信号列表)：这不是只有当信号发生变生时才
//-----执行嘛, 那里写错了啊!!!!
always @(clk, rst_n) begin
if(!rst_n) tp1_r <= 1'b0;
else tp1_r <= ~tp1_r;
end

always @(clk or rst_n) begin
if(!rst_n) tp2_r <= 1'b0;
else tp2_r <= ~tp2_r;
end

//----------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
if(!rst_n) tp3_r <= 1'b0;
else tp3_r <= ~tp3_r;
end

always @(posedge clk, negedge rst_n) begin
if(!rst_n) tp4_r <= 1'b0;
else tp4_r <= ~tp4_r;
end

//----------------------------------------------------------
assign tp1 = tp1_r;
assign tp2 = tp2_r;
assign tp3 = tp3_r;
assign tp4 = tp4_r;

endmodule