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3-5 （1）条件赋值语句

LIBRARY IEEE;

    USE IEEE.STD_LOGIC_1164.ALL;

    USE IEEE.STD_LOGIC_UNSIGNED.ALL; --为使用类型转换函数，打开此程序包。

    ENTITY decoder3to8 IS

      port(   DIN: IN  STD_LOGIC_VECTOR(2 DOWNTO 0);

              DOUT: OUT BIT_VECTOR(7 DOWNTO 0));

    END decoder3to8;

    ARCHITECTURE behave OF decoder3to8 IS

    BEGIN

      WITH CONV_INTEGER(DIN) SELECT

      DOUT<="00000001" WHEN 0,

            "00000010" WHEN 1,

            "00000100" WHEN 2,

            "00001000" WHEN 3,

            "00010000" WHEN 4,

            "00100000" WHEN 5,

            "01000000" WHEN 6,

            "10000000" WHEN 7,

            UNAFFECTED WHEN OTHERS;

    END behave;

（2）case语句

  LIBRARY IEEE;

    USE IEEE.STD_LOGIC_1164.ALL;

    USE IEEE.STD_LOGIC_UNSIGNED.ALL; --为使用类型转换函数，打开此程序包。

    ENTITY decoder3to8 IS

      port(   DIN: IN  STD_LOGIC_VECTOR(2 DOWNTO 0);

              DOUT: OUT BIT_VECTOR(7 DOWNTO 0));

    END decoder3to8;

    ARCHITECTURE behave OF decoder3to8 IS

    BEGIN

      PROCESS (DIN)

      BEGIN

        CASE CONV_INTEGER(DIN) IS

          WHEN 0 => DOUT<="00000001";

          WHEN 1 => DOUT<="00000010";

          WHEN 2 => DOUT<="00000100";

          WHEN 3 => DOUT<="00001000";

          WHEN 4 => DOUT<="00010000";

          WHEN 5 => DOUT<="00100000";

          WHEN 6 => DOUT<="01000000";

          WHEN 7 => DOUT<="10000000";

          WHEN OTHERS => NULL;

        END CASE;

      END PROCESS;

    END behave;

（3）if-else 语句

LIBRARY IEEE;

    USE IEEE.STD_LOGIC_1164.ALL;

    USE IEEE.STD_LOGIC_UNSIGNED.ALL; --为使用类型转换函数，打开此程序包。

    ENTITY decoder3to8 IS

      port(   DIN: IN  STD_LOGIC_VECTOR(2 DOWNTO 0);

              DOUT: OUT BIT_VECTOR(7 DOWNTO 0));

    END decoder3to8;

    ARCHITECTURE behave OF decoder3to8 IS

    BEGIN

      PROCESS (DIN)

      BEGIN

      IF    CONV_INTEGER(DIN)=0 THEN DOUT<="00000001";

      ELSIF CONV_INTEGER(DIN)=1 THEN DOUT<="00000010";

      ELSIF CONV_INTEGER(DIN)=2 THEN DOUT<="00000100";

      ELSIF CONV_INTEGER(DIN)=3 THEN DOUT<="00001000";

      ELSIF CONV_INTEGER(DIN)=4 THEN DOUT<="00010000";

      ELSIF CONV_INTEGER(DIN)=5 THEN DOUT<="00100000";

      ELSIF CONV_INTEGER(DIN)=6 THEN DOUT<="01000000";

      ELSIF CONV_INTEGER(DIN)=7 THEN DOUT<="10000000";

      END IF;

      END PROCESS;

    END behave;

（4）移位操作符

LIBRARY IEEE;

    USE IEEE.STD_LOGIC_1164.ALL;

    USE IEEE.STD_LOGIC_UNSIGNED.ALL; --为使用类型转换函数，打开此程序包。

    ENTITY decoder3to8 IS

      port(   DIN: IN  STD_LOGIC_VECTOR(2 DOWNTO 0);

              DOUT: OUT BIT_VECTOR(7 DOWNTO 0));

    END decoder3to8;

    ARCHITECTURE behave OF decoder3to8 IS

    BEGIN

      DOUT<="00000001" SLL CONV_INTEGER(DIN); --被移位部分是常数

    END behave;

3-14

 LIBRARY  IEEE;

    USE IEEE.STD_LOGIC_1164.ALL;

    USE IEEE.STD_LOGIC_UNSIGNED.ALL;

    ENTITY vote_7 IS

      PORT( DIN:  IN STD_LOGIC_VECTOR(6 DOWNTO 0);--7位表决输入(1:同意，0:不同意)

            G_4: OUT STD_LOGIC;                   --超过半数指示

           CNTH: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));--表决结果统计数

    END vote_7;

    ARCHITECTURE BHV OF vote_7 IS

    BEGIN

      PROCESS(DIN)

        VARIABLE Q: STD_LOGIC_VECTOR(2 DOWNTO 0);

      BEGIN

        Q:="000";

        FOR n IN 0 TO 6 LOOP  -- n是LOOP的循环变量

          IF(DIN(n)='1') THEN Q:=Q+1; END IF;

        ENDLOOP;

        CNTH<=Q;

        IF Q>=4 THEN G_4<='1'; ELSE G_4<='0'; END IF;

      END PROCESS;

    END BHV;