EEPW论坛

想請問各位前輩一下，不知各位有沒有遇過這樣的問題，就是我想把flash memory的程序搬移至SDRAM,我的程序可以跑，所以我想我的flash memory是正常的，我也有寫過sdram的測試程序，它也是測試過的，但只要我把flash的程式搬移至sdram，然後比對看看data對不對，但結果總是錯誤的，請問各位經驗豐富的前輩，這會是什麼樣的問題呢??以下為我的程序，我查了很久還是沒有查到，麻煩各位開導一下，謝謝了~! AREA GPIO, CODE, READONLY ENTRY start LDR r0, =0xf0000008 LDR r1, =0x0 ;/* System Clock Dividing by 0 - non-divided clock is used */ STR r1, [r0]

LDR r0, =0xf0000000 ;/* Clear all SYSCFG except REMAP, BIG(Read-only) */ LDR r1, [r0] AND r1, r1, #0x100 STR r1, [r0]

LDR r0, =0xf0000018 LDR r1, =0x330 ;/* Ethernet controllers have highest arbitor priority */ LDR r1, =0x000 STR r1, [r0]

LDR r0, =0xf000000c ;/* All Clock Enable */ LDR r1, =0x00000000 STR r1, [r0]

LDR r0, =0xf0140008 LDR r1, =0xffffffff ;/* All Interrupt Disable */ STR r1, [r0] LDR r0, =0xf014000c LDR r1, =0x8000007f ;/* All Interrupt Disable */ STR r1, [r0]

LDR r0, =0xf0140000 ;/* All IRQ Mode */ LDR r1, =0 STR r1, [r0] LDR r0, =0xf0140004 ;/* All IRQ Mode */ STR r1, [r0]

;/* ; * 2. SDRAM & OTHER MEMORY CONFIGURATION ; * reference User's Manual, MEMORY CONTROLLER chapter, SDRAM initialization sequence ; */ ; /* ; * <1 > Wait 200us to allow SDRAM power and clocks to stabilize. ; * Wait Time =(fMCLK/MHz)*200 ; */ LDR r0, =50*200 wait1 SUBS r0, r0,#1 BNE wait1

; /* ; * <2> PALL COMMAND SET: ; * Program the INIT[1:0] to 01(PALL). ; */ LDR r0, =0xf0020004 LDR r1, =0x00000001 STR r1, [r0]

; /* ; * <3> Every 15 CLOCK CYCLE REFRESH ; * Write 0xF into the refresh timer register. ; */ LDR r0, =0xf0020008 LDR r1, =0x00000020 STR r1, [r0]

; /* ; * <4> WAIT FUNCTION: ; * Wait for a time period equivalent to 120 clock cycles (8 refresh cycles). ; */ LDR r1, =0x78 wait2 SUBS r1, r1,#1 BNE wait2

; /* ; * <5> NORMAL REFRESH CYCLE ; * Normal operational value into the refresh timer. ; * Common refresh time 15.6 usec ; * SDRAM refresh time = fMCLK*15 + (6*fMCLK)/10 ; */ LDR r1, =(50*15 + (6*50)/10) STR r1, [r0]

; /* ; * <6> Program CFGREG to their normal operation values ; */ LDR r0, =0xf0020000 LDR r1, =0x00058a6e STR r1, [r0]

; /* ; *<7> MRS COMMAND SET ; * Program the INIT[1:0] to 10. This automatically issues a MRS command to the SDRAM. ; */ LDR r0, =0xf0020004 LDR r1, =0x00000002 STR r1, [r0]

; /* ; * <8> SyncDRAM Configration Register Setting ; * Program the INIT[1:0] to 00. The controller enters the normal mode. ; */ LDR r0, =0xf0020004 LDR r1, =0x00000000 STR r1, [r0]

; /* ; * <9> Program CMDREG and WBTOREG to their normal operation values ; */ LDR r0, =0xf0020004 LDR r1, =0x00000004 STR r1, [r0] LDR r0, =0xf002000c LDR r1, =0x00000000 STR r1, [r0]

; /* ; * Initialize Memory Controller for EEPROM/FLASH/SRAM ; */ ; ADRL r0, MEMCON_INITTBL ; ldmia r0, {r1-r10} ; ldr r0, =ASIC_BASE + 0x10000 /* B0CON offset : 0x10000 */ ; stmia r0, {r1-r10}

LDR r0, =0xf0010000 LDR r1, =0x4514e488 STR r1, [r0] LDR r0, =0xf0010004 LDR r1, =0x8514e488 STR r1, [r0] MRS r0,cpsr BIC r0,r0,#0x1f ORR r0,r0,#0x13 MSR cpsr_cxsf,r0

MRC p15, 0, r0, c1, c0, 0 BIC r0, r0, #0x1 ;/* Protection Off */ MCR p15, 0, r0, c1, c0, 0

MRC p15, 0, r1, c1, c0, 0 ;/* Read CP15 Reg, C1(Control Register) */ LDR r0, =0xc0000080 BIC r1, r1, r0 ;/* Clear Clocking Mode bit, Endian bit */

LDR r0, =0xf0000010 LDR r0, [r0] ;/* CLCOK MODE from MCU input setting */ AND r0, r0, #0xc0000000 ORR r1, r1, r0 LDR r0, =0xf0000000 LDR r0, [r0] ;/* ENDIAN from MCU input setting */ AND r0, r0, #0x10000 MOV r0, r0, LSR #9 ORR r1, r1, r0 MCR p15, 0, r1, c1, c0, 0 ;/* Set CP15, C1 with CLOCK MODE, ENDIAN MODE */ LDR r0,=0xf0030000 LDR r1,=0x00000000 STR r1,[r0] ; config IOPMOD1

;************** /* relocate armboot to RAM*/ LDR r0, =0x00000000 ;/* r0 <- current position of code */ LDR r2, =0x00000400 LDR r1, =0x40000000 ;/* r1 <- destination address */

; /* r0 = source address ; * r1 = target address ; * r2 = source end address*/

copy_loop LDR r3,[r0],#0x4 STR r3,[r1],#0x4 CMP r0, r2 BNE copy_loop

;*************************check copy data LDR r0, =0x00000000 ; <---------------------此段為檢查copy的data是否正確，但每次都是第二筆就有問題了~~ LDR r2, =0x00000400 LDR r1, =0x40000000 wait4 LDRB r3,[r0],#0x1 LDR r7,[r1],#0x4 CMP r7, r3 BNE ErrorOuput CMP r0, r2 BNE wait4

loop LDR r2,=0xf003001c LDR r3,=0x00000001 STR r3,[r2] nop nop nop nop LDR r2,=0xf003001c LDR r3,=0x00000000 STR r3,[r2] nop nop nop nop

b loop ErrorOuput LDR r2,=0xf003001c LDR r3,=0x00000002 STR r3,[r2]

nop nop nop nop LDR r2,=0xf003001c LDR r3,=0x00000000 STR r3,[r2] nop nop nop nop b ErrorOuput END