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INCLUDE ../boot_cstarp/boot_16_bit/eb40.inc

AREA cstartup_flash, CODE, READONLY

ENTRY
B InitReset ; reset
undefvec
B undefvec ; Undefined Instruction
swivec
B swivec ; Software Interrupt
pabtvec
B pabtvec ; Prefetch Abort
dabtvec
B dabtvec ; Data Abort
rsvdvec
B rsvdvec ; reserved
irqvec
B irqvec ; reserved
fiqvec
B fiqvec ; reserved

VectorTable
ldr pc, [pc, #&18] ; SoftReset
ldr pc, [pc, #&18] ; UndefHandler
ldr pc, [pc, #&18] ; SWIHandler
ldr pc, [pc, #&18] ; PrefetchAbortHandler
ldr pc, [pc, #&18] ; DataAbortHandler
nop ; Reserved
ldr pc, [pc,#-0xF20] ; IRQ : read the AIC
ldr pc, [pc,#-0xF20] ; FIQ : read the AIC

;- There are only 5 offsets as the vectoring is used.
DCD SoftReset
DCD UndefHandler
DCD SWIHandler
DCD PrefetchAbortHandler
DCD DataAbortHandler
;- Vectoring Execution function run at absolut addresss
SoftReset
b SoftReset
UndefHandler
b UndefHandler
SWIHandler
b SWIHandler
PrefetchAbortHandler
b PrefetchAbortHandler
DataAbortHandler
b DataAbortHandler

;------------------------------------------------------------------------------
;- EBI Initialization Data
;-------------------------

InitTableEBI
DCD EBI_CSR_0
DCD EBI_CSR_1
DCD EBI_CSR_2
DCD EBI_CSR_3
DCD EBI_CSR_4
DCD EBI_CSR_5
DCD EBI_CSR_6
DCD EBI_CSR_7
DCD 0x00000001 ; REMAP command
DCD 0x00000006 ; 6 memory regions, standard read
PtEBIBase
DCD EBI_BASE ; EBI Base Address

;------------------------------------------------------------------------------
;- The reset handler before Remap
;--------------------------------
;- From here, the code is executed from address 0. Take care, as it is linked
;- in 0x100 0000.
;------------------------------------------------------------------------------
InitReset
;- Speed up the Boot sequence
;----------------------------
;- After reset, the number os wait states on chip select 0 is 8. All AT91
;- Evaluation Boards fits fast flash memories, so that the number of wait
;- states can be optimized to fast up the boot sequence.
;------------------------------------------------------------------------------
;- Load System EBI Base address and CSR0 Init Value
ldr r0, PtEBIBase
ldr r1, [pc,#-(8+.-InitTableEBI)]

str r1, [r0] ;r1 -> [r0] ;设置EBI_CSR_0，即NCS0
;--------------------------------
; Call __low_level_init to perform initialization before initializing
; AIC and calling main.
;----------------------------------------------------------------------

;------------------------------------------------------------------------------
;- 使接在P16上面的LED点亮
;----------------------------------------------------
;PIO_BASE EQU 0xffff0000
;PIO_PER EQU 0x00 ;PIO使能寄存器
;PIO_OER EQU 0x10 ;输出使能寄存器
;PIO_SODR EQU 0x30 ;设置输出数据寄存器
;PIO_CODR EQU 0x34 ;清除输出数据寄存器

ldr r0,=PIO_BASE ;r0=0xffff 0000
mov r1,#0x30000
str r1,[r0,#PIO_PER] ;enable p16,p17

mov r1,#0x30000
str r1,[r0,#PIO_OER] ;enable output register

mov r1,#0x20000
str r1,[r0,#PIO_CODR] ;clear p17

mov r1,#0x10000
str r1,[r0,#PIO_CODR] ;clear p16

;------------------------------------------------------------------------------
;- Reset the Interrupt Controller
;--------------------------------
;- Normally, the code is executed only if a reset has been actually performed.
;- So, the AIC initialization resumes at setting up the default vectors.
;------------------------------------------------------------------------------
;- Load the AIC Base Address and the default handler addresses
add r0, pc,#-(8+.-AicData)
ldmia r0, {r1-r4}
str r4, [r1, #AIC_SPU]
str r2, [r1, #AIC_SVR]
add r1, r1, #AIC_SVR
mov r0, #31 ; counter
LoopAic1
str r3, [r1, r0, LSL #2]
subs r0, r0, #1 ; do not save FIQ
bhi LoopAic1

b EndInitAic

;- Default Interrupt Handlers
AicData
DCD AIC_BASE ; AIC Base Address

;------------------------------------------------------------------------------
;- Default Interrupt Handler
;------------------------------------------------------
;- These function are defined in the AT91 library. If you want to change this
;- you can redifine these function in your appication code
;------------------------------------------------------------------------------
IMPORT at91_default_fiq_handler
IMPORT at91_default_irq_handler
IMPORT at91_spurious_handler
PtDefaultHandler
DCD at91_default_fiq_handler
DCD at91_default_irq_handler
DCD at91_spurious_handler
EndInitAic

;------------------------------------------------------------------------------
;- Setup Exception Vectors in Internal RAM before Remap
;------------------------------------------------------
;- Copy the ARM exception vectors

mov r8, #RAM_BASE_BOOT ; @ of the hard vector in internal RAM 0x300000 = r8
add r9, pc,#-(8+.-VectorTable) ; @ where to read values (relative) r9=0x0000 0020
ldmia r9!, {r0-r7} ; read 8 vectors
stmia r8!, {r0-r7} ; store them
ldmia r9!, {r0-r4} ; read 5 absolute handler addresses
stmia r8!, {r0-r4} ; store them

;------------------------------------------------------------------------------
;- Initialise the Memory Controller
;----------------------------------
;- That''s principaly the Remap Command. Actually, all the External Bus
;- Interface is configured with some instructions and the User Interface Image
;- as described above. The jump "mov pc, r12" could be unread as it is after
;- located after the Remap but actually it is thanks to the Arm core pipeline.
;- The IniTableEBI addressing must be relative .
;- The PtInitRemap must be absolute as the processor jumps at this address
;- immediatly after the Remap is performed.
;- Note also that the EBI base address is loaded in r11 by the "ldmia".
;------------------------------------------------------------------------------
;- Copy the Image of the Memory Controller
sub r10, pc,#(8+.-InitTableEBI) ; get the address of the chip select register image
ldr r12, PtInitRemap ; get the real jump address ( after remap )

;- Jump to ROM at its new address
mov pc, r12 ; jump and break the pipeline
PtInitRemap
DCD InitRemap ; address where to jump after REMAP

;------------------------------------------------------------------------------
;- The Reset Handler after Remap
;-------------------------------
;- From here, the code is executed from its link address, ie. 0x100 0000.
;------------------------------------------------------------------------------
;InitRemap

;------------------------------------------------------------------------------
;- Stack Sizes Definition
;------------------------
;- Interrupt Stack requires 3 words x 8 priority level x 4 bytes when using
;- the vectoring. This assume that the IRQ_ENTRY/IRQ_EXIT macro are used.
;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
;- Fast Interrupt is the same than Interrupt without priority level.
;- Other stacks are defined by default to save one word each.
;- The System stack size is not defined and is limited by the free internal
;- SRAM.
;- User stack size is not defined and is limited by the free external SRAM.
;------------------------------------------------------------------------------

IRQ_STACK_SIZE EQU (3*8*4) ; 3 words per interrupt priority level
FIQ_STACK_SIZE EQU (3*4) ; 3 words
ABT_STACK_SIZE EQU (1*4) ; 1 word
UND_STACK_SIZE EQU (1*4) ; 1 word

;------------------------------------------------------------------------------
;- Top of Stack Definition
;-------------------------
;- Fast Interrupt, Interrupt, Abort, Undefined and Supervisor Stack are located
;- at the top of internal memory in order to speed the exception handling
;- context saving and restoring.
;- User (Application, C) Stack is located at the top of the external memory.
;------------------------------------------------------------------------------

TOP_EXCEPTION_STACK EQU RAM_LIMIT ; Defined in part 在part部分定义
TOP_APPLICATION_STACK EQU EXT_SRAM_LIMIT ; Defined in Target 在targets部分定义

;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------------
ldr r0, =TOP_EXCEPTION_STACK ;设置栈顶

;- Set up Fast Interrupt Mode and set FIQ Mode Stack
msr CPSR_c, #ARM_MODE_FIQ:OR:I_BIT:OR:F_BIT
mov r13, r0 ; Init stack FIQ
sub r0, r0, #FIQ_STACK_SIZE

;- Set up Interrupt Mode and set IRQ Mode Stack
msr CPSR_c, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT
mov r13, r0 ; Init stack IRQ
sub r0, r0, #IRQ_STACK_SIZE

InitRemap

;PC=0x0000 0148

;- Set up Abort Mode and set Abort Mode Stack
msr CPSR_c, #ARM_MODE_ABORT:OR:I_BIT:OR:F_BIT ;cpsr=nZCvqIFt_Abort(0x6000 00d7) , r13=0x0000 0000
;spsr=nzcvqift_Res(0x0000 0000)
mov r13, r0 ; Init stack Abort r13=0x0100 252a
sub r0, r0, #ABT_STACK_SIZE ;r0 =0x0100 2526

;- Set up Undefined Instruction Mode and set Undef Mode Stack
msr CPSR_c, #ARM_MODE_UNDEF:OR:I_BIT:OR:F_BIT ;cpsr=nZCvqIFt_Undef(0x6000 00db),r13=0x0000 0000
mov r13, r0 ; Init stack Undef ;r13 =0x0100 2526
sub r0, r0, #UND_STACK_SIZE ;r0 =0x0100 2522

;- Set up Supervisor Mode and set Supervisor Mode Stack
msr CPSR_c, #ARM_MODE_SVC:OR:I_BIT:OR:F_BIT ;cpsr=nZCvqIFt_SVC(0x6000 00d3),r13=0x0000 0000
mov r13, r0 ; Init stack Sup ;r13=0x0100 2522

;------------------------------------------------------------------------------
;- Setup Application Operating Mode and Enable the interrupts
;------------------------------------------------------------
;- System Mode is selected first and the stack is setup. This allows to prevent
;- any interrupt occurence while the User is not initialized. System Mode is
;- used as the interrupt enabling would be avoided from User Mode (CPSR cannot
;- be written while the core is in User Mode).
;------------------------------------------------------------------------------
msr CPSR_c, #ARM_MODE_USER
ldr r13, =TOP_APPLICATION_STACK ; Init stack User r13=0x0000 2000

;------------------------------------------------------------------------------
;- Initialise C variables
;------------------------
;- Note on the Data position :
;- If using the ARMSDT, when no -rw-base option is used for the linker, the
;- data area is mapped after the code. You can map the data either in internal
;- SRAM ( -rw-base=0x40 or 0x34) or in external SRAM ( -rw-base=0x2000000 ).
;------------------------------------------------------------------------------
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise

ldr r0, =|Image$$RO$$Limit| ; Get pointer to ROM data r0=0x0000 2d3c
ldr r1, =|Image$$RW$$Base| ; and RAM copy
ldr r3, =|Image$$ZI$$Base| ; Zero init base => top of initialised data
cmp r0, r1 ; Check that they are different
beq NoRW
LoopRw cmp r1, r3 ; Copy init data
ldrcc r2, [r0], #4
strcc r2, [r1], #4
bcc LoopRw
NoRW ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segment r1=0x30 0268
mov r2, #0
LoopZI cmp r3, r1 ; Zero init 对zi段进行清零
strcc r2, [r3], #4 ; CC/LO 无符号数小于
bcc LoopZI

;------------------------------------------------------------------------------
;- Branch on C code Main function (with interworking)
;----------------------------------------------------
;------------------------------------------------------------------------------
IMPORT main

ldr r0, =main
mov lr, pc
bx r0
ldr r13,=0x00
ldr r0,=0x02000000
bx r0
;------------------------------------------------------------------------------
End
b End

END