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问 Reliable system operation often depends on the quality of the power supplied. Supply voltages that are too low CAN cause faulty operation as the microcontroller, FPGA, or ASIC begin to send bad data to memories or peripheral devices. Too high a voltage CAN damage a device permanently. In addition to providing protection in the event of a voltage fluctuation, users may want to identify the source of the failure.

The application must use a voltage regulator plus a pair of FETs and some resistors to provide power shutoff. The two-wire interface and fault register of the regulator should provide fault-monitoring capability and include EEPROM (4 kbits is the recommended allotment) for maintaining information such as manufacturing and service records.

This voltage regulator monitors three input voltages with voltage thresholds of 4.6, 2.9, and 1.0 V. The Figure 1 circuit shows a configuration that turns off the 3.3-V output if a 5-V supply is too low, or if the 3.3-V supply is too low or too high.



A MOSFET (Q1) is used as the primary pass element, or switch. The MOSFET is a PMOS device that requires a VGS of only 2.5 V to turn on. It then CAN be used on power supplies down to 2.5 V with an RDS(ON) of less than 0.1 O. The regulator controls this FET's gate through a FET (Q3) that has a maximum VGS of 2.5 V. For lower voltages, both the MOSFET and FET may be replaced by a dual MOSFET, such as the Si4913 from Siliconix, which has a VGS of 1.8 V and RDS(ON) (at 1.8 V) of 24 mO.

The regulator's VCC input monitor, which in this example is the Intersil X40435, turns off its open-drain RESET output 200 ms (tPOR) after VCC goes above the threshold of 4.6 V. The V3MON input monitor of the X40435 turns off its open drain V3FAIL output when the 3.3-V supply goes above 2.9 V. When both of these conditions are valid, the gate of the FET (2N7002) is pulled high and turns on, allowing the V2FAIL output to control the gate of the MOSFET (in this example, it's the Si3443). If the tPOR time delay isn't desired on the 5-V input, then the LOWLINE output CAN replace the RESET output.

The V2MON input of the X40435 receives a voltage divided down from the 3.3-V supply. The resistor divider is set such that the V2MON voltage is 1 V when the 3.3-V supply reaches 3.6 V (the overvoltage level). When the 3.3-V supply is below 3.6 V, the V2FAIL output is LOW. This turns on the MOSFET, which supplies power to the load.

When the 3.3-V supply reaches 3.6 V, the V2FAIL output goes HIGH, turning off the output supply. When either the 3.3-V or 5-V supplies drop below their respective thresholds, the 2N7002 device turns off and the Si3443 gate is pulled HIGH, again turning off the load.

The X40435 has a two-wire interface that allows access to the EEPROM and the Fault Detection Register. When the X40435 powers up, it resets all fault bits to zero. Also, any fault condition causes the related bit to reset to zero. Therefore, if the microcontroller checks the fault bits first, before writing them all to ones, it CAN determine what caused the system reset. If, for example, all bits are zero, then the 5-V input supply powered off. If the LV3F bit is zero, then there was a 3.3-V dropout. If the LV2F bit is zero, then the V2MON supply went above its threshold, then dropped back below it—indicating an overvoltage condition. There are also bits to indicate a watchdog timer time-out or a manual reset of the system.

A variation of this circuit is shown in Figure 2. In this circuit, an undervoltage condition on the 3.3-V supply only causes the system to be reset. That is, the 3.3-V supply is not cut off. The 3.3-V supply is turned off to the load only when the 3.3-V input exceeds the maximum limit.



答 1: 顶。