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问 下面是一个用用TIMERA的CCR1，CCR2，分别产生75%，25%的PWM信号的程序，用ACLK 做时钟源，但是老是出现警告“Warning[Pe001]: last line of file ends without a newline”
，不知道为什么，快把我烦死了，各位能帮忙看看吗？是个在TI上面下载的EXAMPLE
// MSP-FET430P140 Demo - Timer_A PWM TA1-2 upmode, 32kHz ACLK
//
// Description; This program will generate a two PWM outputs on P1.2/1.3 using
// Timer_A in an upmode. The value in CCR0, defines the period and the
// values in CCR1 and CCR2 the duty PWM cycles. Using 32kHz ACLK as TACLK,
// the timer period is 15.6ms with a 75% duty cycle on P1.2 and 25% on P1.3.
// ACLK = TACLK = LFXT1 = 32768, MCLK = SMCLK = default DCO ~ 800kHz.
// Normal mode LPM3
// /External watch crystal installed on XIN XOUT is required for ACLK
//
// MSP430F149
// -----------------
// /|\| XIN|-
// | | | 32k
// --|RST XOUT|-
// | |
// | P1.2|--> CCR1 - 75% PWM
// | P1.3|--> CCR2 - 25% PWM
//
// M.Buccini
// Texas Instruments, Inc
// September 2003
// Built with IAR Embedded Workbench Version: 1.26B
// January 2004
// Updated for IAR Embedded Workbench Version: 2.21B
// modified by zy on 06/06/2004
//******************************************************************************

#include <MSP430x14x.h>

void initial_ta_pwm02(void);



void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
initial_ta_pwm02();

_BIS_SR(LPM3_bits); // Enter LPM3

}


void initial_ta_pwm02(void)
{
P1DIR |= 0x0C; //p1.2,p1.3 output
P1SEL |= 0x0C; //p1.2,p1.3 for pwm mode for TA1/2
CCR0=512-1; //PWM peirod 15.6ms/32768=512
CCTL1=OUTMOD_7; //CCR1 reset/set
CCR1= 384; //CCR1 PWM for 75% high level
CCTL2=OUTMOD_7; //CCR2 reset/set
CCR2=128; //CCR2 PWM for 25% high level
TACTL=TASSEL_1+MC_1; //ACLK,up mode
} 答 1: 警告的翻译为：最后行 of 文件末尾 没有新的起始行， 那么在这个文件的最后行再打个回车，有新的起始行就ok了。