问 Protel Design System Design Rule Check
PCB File : Documents\dianlu.PCB
Date     : 22-Sep-2006
Time     : 09:27:18

Processing Rule : Width Constraint (Min=40mil) (Max=40mil) (Prefered=40mil) (Is on net VCC )
   Violation         Track (58625mil,57090mil)(58640mil,57090mil)  TopLayer  Actual Width = 25mil
   Violation         Track (57275mil,55840mil)(57286.142mil,55840mil)  TopLayer  Actual Width = 20mil
   Violation         Track (58485mil,56580mil)(58505mil,56560mil)  TopLayer  Actual Width = 20mil
Rule Violations :3

Processing Rule : Width Constraint (Min=40mil) (Max=40mil) (Prefered=40mil) (Is on net GND )
   Violation         Track (57300mil,55697.441mil)(57300mil,55700mil)  TopLayer  Actual Width = 20mil
   Violation         Track (57286.142mil,55697.441mil)(57300mil,55697.441mil)  TopLayer  Actual Width = 20mil
   Violation         Track (56900mil,55554.882mil)(56920mil,55554.882mil)  TopLayer  Actual Width = 20mil
   Violation         Track (56900mil,55550mil)(56900mil,55554.882mil)  TopLayer  Actual Width = 20mil
   Violation         Track (57300mil,55700mil)(57319mil,55700mil)  TopLayer  Actual Width = 20mil
Rule Violations :5

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )
   Violation         Pad P1-1(60260mil,56500mil)  MultiLayer  Actual Hole Size = 102mil
   Violation         Pad P1-3(60363mil,56686mil)  MultiLayer  Actual Hole Size = 102mil
   Violation         Pad P1-2(60489mil,56500mil)  MultiLayer  Actual Hole Size = 102mil
   Violation         Pad J1-11(59652mil,55507mil)  MultiLayer  Actual Hole Size = 140mil
   Violation         Pad J1-10(60638mil,55507mil)  MultiLayer  Actual Hole Size = 140mil
Rule Violations :5

Processing Rule : Width Constraint (Min=15mil) (Max=15mil) (Prefered=15mil) (On the board )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=10mil) (On the board ),(On the board )
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (On the board ) )
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0


Violations Detected : 13
Time Elapsed        : 00:00:00 答 1: I see