A0–An: External address pins for data/program memory or I/O devices.absolute address: An address that is permanently assigned to a memory location. See also symbolic address.
absolute lister: A debugging tool that accepts linked files as input and creates .abs files as output. These .abs files can be assembled to pro-duce a listing that shows the absolute addresses of object code. Without the tool, an absolute listing can be prepared with the use of many manual operations.
ABU: See autobuffering unit.
ACC: See accumulator.
ACCB: See accumulator buffer.
access stage: The optional third stage of the master processor’s fetch, exe-cute, access (FEA) pipeline, during which memory accesses (load or store operations) occur. (TMS320C8x)
ACCH: See accumulator high byte.
ACCL: See accumulator low byte.
accumulator (ACC): A register that temporarily stores the results of an arithmetic logic unit (ALU) operation and provides an input for subse-quent ALU operations. The ACC is accessible in two halves: accumula-tor high (ACCH) and accumulator low (ACCL).
accumulator buffer (ACCB): A register that temporarily stores the contents of the accumulator (ACC). The ACCB has a direct path back to the arith-metic logic unit (ALU) and can be arithmetically or logically acted upon with the ACC.
accumulator high byte (ACCH): The most significant bits stored in the accumulator (ACC). See also accumulator.
accumulator low byte (ACCL): The least significant bits stored in the accumulator (ACC). See also accumulator.
active time: The time intervals of a display frame that are not in blanking.
The time intervals in which pixels are displayed. See also blanking.(TMS320C8x)
active window: The window that is currently selected for moving, sizing,editing, closing, or some other function.
A/D: See analog-to-digital.
ADC: See analog-to-digital converter.
ADC bit: See detect complete bit.
address: The logical location of program code or data stored in memory.
addressing mode: The method by which an instruction interprets its operands to acquire the data it needs.
address stage: The second stage of the parallel processor’s fetch, address execute (FAE) pipeline during which addresses are calculated and supplied to the crossbar. (TMS320C8x)
address unit: Hardware on the parallel processor that computes a bit address during each cycle. Each parallel processor has two address
units: a global address unit and a local address unit. (TMS320C8x)
address unit arithmetic: The parallel processor’s use of the local and global address units to perform general-purpose arithmetics in parallel with the data unit. The computed address is not used for memory access, bu is stored in the estination register. (TMS320C8x)
address visibility (AVIS) bit: A bit field that allows the internal program address to appear at the external address pins. This enables the interna program address to be traced and the interrupt vector to be decoded in ) signal when the inter-
conjunction with the interrupt acknowledge (IACK rupt vectors reside in on-chip memory. At reset, AVIS = 0. (TMS320C5x
administrative privileges: Authority to set software and hardware access includes access and privileges to install, manage, and maintain system and application software and directories on a network server or individua computer systems.
ADTR: Asynchronous data transmit and receive register. See also receive (ADTR) register.
AFB: See auxiliary register file bus.
aggregate type: A C data type, such as a structure or an array, in which a variable is composed of multiple other variables, called members.
AIC: See analog interface circuit.
A-Law companding: See companded.
alias disambiguation: A technique that determines when two pointer expressions cannot point to the same location, allowing the compiler to freely optimize such expressions. (TMS320C6200)
aliasing: 1) A method of customizing debugger commands; aliasing provides a shorthand method for entering often-used command strings.
2) A method of accessing a single data object in more than one way, as when a pointer points to a named object. The optimizer has logic to detect aliasing, but aliasing can cause problems for the optimizer. 3) Aliasing occurs when a single object can be accessed in more than one way, such as when two pointers point to a single object. It can disrupt optimization,
because any indirect reference could refer to any other object.
alignment: A process in which the linker places an output section at an address that falls on an n-byte boundary, where n is a power of 2. You can specify alignment with the SECTIONS linker directive.
allocation: A process in which the linker calculates the final memory addresses of output sections.
allocation node: The processor node into which an internode message is allocated.
ALU: See arithmetic logic unit.
ALU function: For the parallel processor, an action performed on the three inputs to the arithmetic logic unit (ALU), which includes any arithmetic or Boolean combination of the three inputs, as well as mixed arithmetic and Boolean functions. (TMS320C8x)
ALU function modifier: For the parallel processor, a 4-bit code that speci-fies modifications to the functions performed by the arithmetic logic unit (ALU) data path (such as carry-in or multiple arithmetic). These function modifiers are specified in the opcode or in the D0 register, depending on the application. (TMS320C8x)
ALU operation: For the parallel processor, an action performed by the arithmetic logic unit (ALU) data path (that is, the result of the ALU function,the operation class, and any function modifiers). (TMS320C8x)
analog interface circuit (AIC): Integrated circuit that performs serial analog-to-digital (A/D) and digital-to-analog (D/A) conversions.