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    library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
entity h_adder2 is
  port(a,b:in std_logic;
       so,co:out std_logic);
end;
architecture bhv of h_adder2 is
  signal ab:std_logic_vector(1 downto 0);
  begin
  ab<=a&b;
  process(ab)
  begin
  case ab is
  when "00"=>so<='0';co<='0';
  when "01"=>so<='1';co<='0';
  when "10"=>so<='1';co<='0';
  when "11"=>so<='0';co<='1';
  end case;
  end process;
end;
 
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
  port(a,b:in std_logic;
         c:out std_logic);
end;
architecture bhv of or2a is
  begin
  c<=a or b;
end;          

library ieee;
use ieee.std_logic_1164.all;
entity f_adder is
  port(ain,bin,cin:in std_logic;
          sum,count:out std_logic);
end;
architecture bhv of f_adder is
  component h_adder
      port(a,b:in std_logic;
           co,so:out std_logic);
   end component;
 
  component or2a
      port(a,b:in std_logic;
             c:out std_logic);
    end component;
   signal d,e,f:std_logic;
   begin
   u1:h_adder port map(a=>ain,b=>bin,co=>d,so=>e);
   u2:h_adder port map(a=>e,b=cin,co=>f,so=>sum);
   u3:or2a port map(a=>d,b=>f,c=>count);
   end;          

    这个程序编译时倒数第三行出错  错误提示为Error (10437): VHDL Association List error at f_adder.vhd(53): positional associations must be listed before named associations

    麻烦各位网友帮忙解释一下撒！！！