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鱼板寄存器写入问题

菜鸟
2003-09-26 17:34:00    评分
这是rominit.S开始的一段,当运行到下面斜杠的位置就飞了,我通过屏蔽代码调试发现第一个寄存器是可以设的,后面的就不行了,请大侠指点 /* disable interrupts in CPU and switch to SVC32 mode */ MRS r1, cpsr /* From cpsr */ BIC r1, r1, #MASK_MODE /* clear mode */ ORR r1, r1, #MODE_SVC32 | I_BIT | F_BIT /* set supervisor mode & clear IRQ and FIQ */ MSR cpsr, r1 /* To cpsr */ MOV r13, r0 /* Save starttype in r13 so that r0 can be used for other purposes */ /* * CPU INTERRUPTS DISABLED * disable individual interrupts in the interrupt controller */ LDR r2, L$_SBCARM7Intmsk /* R2->interrupt controller */ MVN r1, #0 /* &FFFFFFFF */ STR r1, [r2] /* disable all interrupt sources */ /* * If not BOOT_COLD, bypass memory configuration, memory region * switching etc. */ CMP r0, #BOOT_COLD BNE JumpPos LDR r0, L$_SBCARM7Syscfg LDR r1, L$_SysCfgSdram STR r1, [r0] /* Cache,WB disable */ LDR r1, L$_SystemInitDataSDRAM LDR r2, L$_SystemInitDataSDRAM + 0x04 LDR r3, L$_SystemInitDataSDRAM + 0x08 LDR r4, L$_SystemInitDataSDRAM + 0x0c LDR r5, L$_SystemInitDataSDRAM + 0x10 LDR r6, L$_SystemInitDataSDRAM + 0x14 LDR r7, L$_SystemInitDataSDRAM + 0x18 LDR r8, L$_SystemInitDataSDRAM + 0x1c LDR r9, L$_SystemInitDataSDRAM + 0x20 LDR r10,L$_SystemInitDataSDRAM + 0x24 LDR r11,L$_SystemInitDataSDRAM + 0x28 LDR r12,L$_SystemInitDataSDRAM + 0x2c LDR r0, L$_SBCARM7Extdbwth /* Extdbwth Offset : 0x3010 */ STMIA r0, {r1-r12} /*只能运行到这里*////////////////////////////////////////////// LDR r1, L$_ClkCon LDR r0, L$_SBCARM7ClkCon /* CLKCON Offset : 0x3000 */ STR r1, [r0] LDR r1, L$_ExtACon LDR r2, L$_ExtACon + 0x04 LDR r0, L$_SBCARM7ExtACon /* EXTACON Offset : 0x3008 */ STMIA r0, {r1-r2}



关键词: 鱼板     寄存器     写入     问题     SystemInitDa    

菜鸟
2003-09-26 19:05:00    评分
2楼
已经搞定了,是寄存器地址设置问题 似乎Rom0的地址必须设成0

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