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Multiply Your Sampling Rate with Time-Interleaved Data Converters


关键词: interleaving, time-interleaving, high-speed, analog-to-digital converter, high-speed ADC, coarse quantizer, fine quantizer, flash converter, bandwidth limitation, offset error, gain error, mismatches, nonlinearities, clock phase noise, clock jitter 


Abstract: Interleaving multiple analog-to-digital converters (ADCs) is usually performed with the intent to increase a converters effective sample rate, especially if there are no or only few off-the-shelf ADCs available that fulfill the desired sample, linearity and AC requirements of such applications. However, time-interleaving data converters is not an easy task, because even with perfectly linear components, gain/offset mismatches and timing errors can cause undesired spurs in the output spectrum. The following article provides valuable insight into the theoretical approach of time-interleaved analog-to-digital converters and the kind of roadblocks (and how to compensate for them) a designer usually encounters when building a time-interleaved system. 



 Multiply Your Sampling Rate with Time-Interleaved Data Converters.pdf