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共45条 4/5 |‹ ‹ 1 2 3 4 5 › 跳转至页
wenyangzeng
工程师
2012-11-13 22:25:36     打赏
31楼

进程12、TLC549ADC

       有点可惜，接口板的ADC芯片只有8位转换精度。板上的那只多圈电位器就取消了，焊上一只3脚插座，外接一只电位器代用，省得再对PCB板进行动手术。

 ADC_CLK转换时钟从50MHZ晶振分频成1MHZ得到：

@(posedge CLK or negedge RSTn) //rAD_CLK = 1MHz
 begin
    if(!RSTn)
        begin
            rDCLK_DIV <= 1'b0;
           rAD_CLK <= 1'b0;
       end
 else
      if(rDCLK_DIV < 6'd50) rDCLK_DIV <= rDCLK_DIV+1'b1;
        else
           begin
               rDCLK_DIV <= 0;
             rAD_CLK <= ~rAD_CLK;
          end
  end
/**************************************
// 读出的8位ADC值存放在result中：

rAD_CLK : 1'b0;
reg[7:0] rData_reg;
always @(negedge rAD_CLK)
begin
  if(rCount >= 5'd2 && rCount <= 5'd9) 
     begin
       rData_reg[0] <= AD_DATA;
       rData_reg[7:1] <= rData_reg[6:0];
     end
  else  result <= rData_reg;
 end
显示部分代码就省略了

 
                      逻辑框图



                      IO分配图


   
                                  运行结果
      感觉转换结果的个位数不是很稳定。

点击下载tlc549_top.rar


评论
wenyangzeng
工程师
2012-11-25 20:55:59     打赏
32楼

进程13、VGA彩条

         练习中接口板上的VGA接口使用了10、31、37（RGB)和4、6（行场同步）共5条信号线。运行后在屏幕上显示8条水平彩条。由彩条控制模块和同步控制模块组合而成。

彩条控制模块
module vga_control_module
(
    CLK, RSTn,
  Ready_Sig, Column_Addr_Sig, Row_Addr_Sig,
  Red_Sig, Green_Sig, Blue_Sig
);
    input CLK;
  input RSTn;
  input Ready_Sig;
  input [10:0]Column_Addr_Sig;
  input [10:0]Row_Addr_Sig;
  output Red_Sig;
  output Green_Sig;
  output Blue_Sig;
  reg isRectangle;
  always @ ( posedge CLK or negedge RSTn )
      if( !RSTn )
        isRectangle <= 1'b0;
    else if( Column_Addr_Sig > 11'd0 && Row_Addr_Sig < 11'd600 )
            isRectangle <= 1'b1;
    else
        isRectangle <= 1'b0;
     wire color0,color1,color2,color3,color4,color5,color6,color7;
   assign color7 = ( (Row_Addr_Sig>=0  ) && (Row_Addr_Sig<=75) );
   assign color6 = ( (Row_Addr_Sig>=75) && (Row_Addr_Sig<=150) );
   assign color5 = ( (Row_Addr_Sig>=150) && (Row_Addr_Sig<=225) );
   assign color4 = ( (Row_Addr_Sig>=225) && (Row_Addr_Sig<=300) );
   assign color3 = ( (Row_Addr_Sig>=300) && (Row_Addr_Sig<=375) );
   assign color2 = ( (Row_Addr_Sig>=375) && (Row_Addr_Sig<=450) );
   assign color1 = ( (Row_Addr_Sig>=450) && (Row_Addr_Sig<=525) );
   assign color0 = ( (Row_Addr_Sig>=525) && (Row_Addr_Sig<=600) );
  assign Red_Sig = Ready_Sig && isRectangle ?  (color0 | color3 | color4 | color6 ): 1'b0;
  assign Green_Sig = Ready_Sig && isRectangle ? (color1 | color3 | color5 | color6) : 1'b0;
  assign Blue_Sig = Ready_Sig && isRectangle ? (color2 | color4 | color5 | color6 ) : 1'b0;
endmodule
/****************************************/
同步控制模块

 module sync_module
(
    CLK, RSTn,
  VSYNC_Sig, HSYNC_Sig, Ready_Sig,
  Column_Addr_Sig, Row_Addr_Sig
);

    input CLK;
  input RSTn;
  output VSYNC_Sig;
  output HSYNC_Sig;
  output Ready_Sig;
  output [10:0]Column_Addr_Sig;
  output [10:0]Row_Addr_Sig;
  reg [10:0]Count_H;   
  reg [9:0]Count_V;   
  always @ ( posedge CLK or negedge RSTn )
      if( !RSTn ) Count_H <= 11'd0;
  else if( Count_H == 11'd1039 )   Count_H <= 11'd0;
  else  Count_H <= Count_H + 1'b1;
  always @ ( posedge CLK or negedge RSTn )
      if( !RSTn )  Count_V <= 10'd0;
  else if( Count_V == 10'd665 )Count_V <= 10'd0;
  else if( Count_H == 10'd1039 )Count_V <= Count_V + 1'b1;
  reg isReady;
   always @ ( posedge CLK or negedge RSTn )
      if( !RSTn )
        isReady <= 1'b0;
        else if((Count_H > 11'd215) &&( Count_H < 11'd1015 ) &&
           ( Count_V > 10'd32) &&( Count_V < 10'd632 ) )
        isReady <= 1'b1;
    else
        isReady <= 1'b0;
  assign VSYNC_Sig = ( Count_V <= 11'd6 ) ? 1'b0 : 1'b1;
  assign HSYNC_Sig = ( Count_H <= 11'd120 ) ? 1'b0 : 1'b1;
  assign Ready_Sig = isReady; 
  assign Column_Addr_Sig = isReady ? Count_H - 11'd217 : 11'd0;   assign Row_Addr_Sig = isReady ? Count_V - 11'd28 : 11'd0; 
endmodule


 
                                IO分配表



                                显示结果

点击下载 vga_module.rar


评论
djslc
高工
2012-11-25 21:06:17     打赏
33楼
不错，顶起

评论
w013016
助工
2012-11-26 22:50:49     打赏
34楼
学习！！！

评论
51FPGA
高工
2012-11-26 22:52:34     打赏
35楼
不错，继续加油！

评论
wenyangzeng
工程师
2012-12-05 19:40:01     打赏
36楼

进程14、音乐彩灯、警笛声、电子琴

14.1音乐彩灯

        练习中将音乐《铃儿响叮当》自动演奏和LDE灯相结合，组成音乐彩灯。

module music(clk,beep,led);     
input clk;      
output beep;      
output [10:0]led;

reg r_BEEP;      
reg[7:0] r_STATE;       
reg[16:0]r_r_COUNT,r_NOTES;
reg[23:0]r_COUNT1;
reg[10:0]r_r_LED_OUT;

parameter    L_1 = 17'd95566,
  L_2 = 17'd85121,
  L_3 = 17'd75850,           
  L_4 = 17'd71592,
  L_5 = 17'd63776,           
  L_6 = 17'd56818,       
  L_7 = 17'd50618,   
  M_1 = 17'd47774,   
  M_2 = 17'd42568,   
  M_3 = 17'd37919,   
  M_4 = 17'd35791,
  M_5 = 17'd31888,   
  M_6 = 17'd28409,   
  M_7 = 17'd25309,
parameter TIME = 6000000;  
 
assign beep = r_BEEP;   
  
always@(posedge clk)
begin
 r_COUNT <= r_COUNT + 1'b1;    
 if(r_COUNT == r_NOTES)
     begin
        r_COUNT <= 17'h0;     
       r_BEEP <= !r_BEEP;    
     end
end
always @(posedge clk)
begin
 if(r_COUNT1 < TIME)     
      r_COUNT1 = r_COUNT1 + 1'b1;
 else
 begin
     r_COUNT1 = 24'd0;
       if(r_STATE == 8'd120)
          r_STATE = 8'd0;
      else
        r_STATE = r_STATE + 1'b1;

  case(r_STATE)
   8'd1: r_NOTES = L_5;
   8'd3: r_NOTES = M_3;
   8'd5: r_NOTES = M_2;
   8'd7: r_NOTES = M_1;
   8'd9: r_NOTES = L_5;
   8'd13: r_NOTES = 0;
   8'd15: r_NOTES = L_5;
   8'd17: r_NOTES = M_3; 
   8'd19: r_NOTES = M_2;
   8'd21: r_NOTES = M_1;
   8'd23: r_NOTES = L_6;
   8'd27: r_NOTES = 0;
   8'd29: r_NOTES = L_6;
   8'd31: r_NOTES = M_4;
   8'd33: r_NOTES = M_3;
   8'd35: r_NOTES = M_2;
   8'd37: r_NOTES = M_5;
   8'd39: r_NOTES = 0; 
   8'd41: r_NOTES = M_5;
   8'd42: r_NOTES = 0;    
   8'd45: r_NOTES = M_6;  
   8'd47: r_NOTES = M_5;   
   8'd49: r_NOTES = M_4;
   8'd51: r_NOTES = M_2;
   8'd53: r_NOTES = M_1;
   8'd57: r_NOTES = 0;
   8'd58: r_NOTES = M_3;
   8'd59: r_NOTES = 0;
   8'd60: r_NOTES = M_3;
   8'd61: r_NOTES = 0;
   8'd62: r_NOTES = M_3; 
   8'd64: r_NOTES = 0;
   8'd65: r_NOTES = M_3;
   8'd66: r_NOTES = 0;
   8'd67: r_NOTES = M_3;
   8'd68: r_NOTES = 0;
   8'd69: r_NOTES = M_3; 
   8'd70: r_NOTES = 0;
   8'd73: r_NOTES = M_3;    
   8'd75: r_NOTES = M_5;
   8'd77: r_NOTES = M_1;
   8'd79: r_NOTES = M_2;    
   8'd81: r_NOTES = M_3;  
   8'd85: r_NOTES = 0;
   8'd86: r_NOTES = M_4;
   8'd87: r_NOTES = 0;
   8'd88: r_NOTES = M_4;
   8'd89: r_NOTES = 0;
   8'd90: r_NOTES = M_4;
   8'd92: r_NOTES = 0;
   8'd94: r_NOTES = M_3;
   8'd95: r_NOTES = 0;
   8'd96: r_NOTES = M_3;
   8'd97: r_NOTES = 0;
   8'd98: r_NOTES = M_3; 
   8'd100: r_NOTES = 0;
   8'd102: r_NOTES = M_5;
   8'd103: r_NOTES = 0; 
   8'd104: r_NOTES = M_5;
   8'd105: r_NOTES = M_4;
   8'd107: r_NOTES = M_2;
   8'd109: r_NOTES = M_1;
   8'd113: r_NOTES = 0; 
  endcase
 end
end

always @(posedge clk)
begin
  case (r_NOTES)
    L_5: r_LED_OUT = 11'b11101010100;
    L_6: r_LED_OUT = 11'b11011101001;
    M_1: r_LED_OUT = 11'b11110100111;
    M_2: r_LED_OUT = 11'b10101001110;
    M_3: r_LED_OUT = 11'b11010011101;
    M_4: r_LED_OUT = 11'b10100111011;
    M_5: r_LED_OUT = 11'b01001110110;
    M_6: r_LED_OUT = 11'b10011101111;
    M_7: r_LED_OUT = 11'b00111011101;
    0:r_LED_OUT  = 11'b11111111111;
    endcase
end
assign led=r_LED_OUT;
endmodule


                           IO分配图



                           运行结果
点击下载music.rar


14.2 警车鸣笛声

module beep(CLK, BEEP);   
input CLK;   
output BEEP;   
reg BEEP; 
reg [27:0] tone;
    reg [14:0] counter;
always @(posedge CLK)
begin
    tone <= tone+1;
end     
wire [6:0] fastsweep = (tone[22] ? tone[21:15] : ~tone[21:15]);   
wire [6:0] slowsweep = (tone[25] ? tone[24:18] : ~tone[24:18]);   
wire [14:0] clkdivider = {2'b01, (tone[27] ? slowsweep : fastsweep), 6'b000000};   
 
always @(posedge CLK)
 begin
 if(counter==0) counter <= clkdivider;
 else counter <= counter-1;
 end     
always @(posedge CLK)
begin
if(counter==0)
BEEP <= ~BEEP;
end    
endmodule   



                      I/O分配

点击下载beep.rar

14.3 电子琴

module key_music(CLK,KEY,BEEP,LED);
input CLK;
input[7:0]KEY;
output BEEP;
output[7:0]LED;
reg r_BEEP;
reg[7:0]r_LED;
reg[7:0]r_KEY;
reg[22:0]r_count,r_count_end;
reg r_KEY_flag;

  initial r_KEY_flag = 1'b0;
  always@(posedge CLK)
   begin
     r_count=r_count+1;
     if(r_count == r_count_end)
  begin
   r_count=0;
    if(r_KEY_flag==1'b1)
    r_BEEP= ~r_BEEP;
   else
    r_BEEP = 1'b0;
   end
  end
 always@(r_count[10:9])
 begin
   r_KEY = KEY;
    if(r_KEY!=8'hff)r_KEY_flag = 1'b1;
    else
  r_KEY_flag = 1'b0;
  case (r_KEY)
   8'b11111110:r_count_end = 20'd47774;
   8'b11111101:r_count_end = 20'd42568;
   8'b11111011:r_count_end = 20'd37919;
   8'b11110111:r_count_end = 20'd35791;
   8'b11101111:r_count_end = 20'd31888;
   8'b11011111:r_count_end = 20'd28409;
   8'b10111111:r_count_end = 20'd25309;
   8'b01111111:r_count_end = 20'd23912;
      default r_count_end = 20'hfffff;
  endcase
 end
assign BEEP=r_BEEP;
assign LED = r_KEY;
endmodule



               I/O分配表

点击下载key_music.rar


评论
wenyangzeng
工程师
2012-12-18 20:01:07     打赏
37楼

进程15、DS18B20温度计

     单总线的DS18B20硬件连接确实简单，软件读写过程却挺复杂的，花费了不少的时间。部分代码：

//----------芯片复位-----------
 begin        
  cnt <= cnt + 1;
   if(cnt < 'd500)
     begin
        link <= 1;
        dq_out <= 0;
   end
  else if(cnt < 'd1000)
   begin
       link <= 0;
   end
  else  begin
      cnt <= 0;
     state <= WRITE_CC1;
     data_w <= 8'hcc;
     cnt_bit <= 0;
   end
  end 
   
//-------写命令44H---------------
 begin          
   cnt <= cnt + 1;
      if(cnt < 'd5)
         begin
    l       ink <= 1;
           dq_out <= 0;
        end 
    else if(cnt < 'd60)
     begin
          dq_out <= data_w[cnt_bit];
     end
    else if(cnt < 'd65)
       begin
           link <= 0;
      end
    else begin
        cnt <= 0;
        cnt_bit <= cnt_bit + 1;
            if(cnt_bit == 'd7)
               begin
                cnt_bit <= 0;
                state <= WAIT_800MS;
              end
     end
    end
//-------------读温度--------------
 begin                
cnt <= cnt + 1;
   if(cnt < 'd3)
      begin
        link <= 1;
        dq_out <= 0;
     end
  else if(cnt == 'd3)
      link <= 0;
  else if(cnt == 'd12)
       data_r[cnt_bit] <= dq_in;
 else if(cnt > 'd65)
 begin
     cnt <= 0;
     cnt_bit <= cnt_bit + 1;
      if(cnt_bit == 'd7)
         begin
          cnt_bit <= 0;
         temp[15:8] <= data_r;
         state <= RESET1;
    end
  end

end 

//-------------BCD码处理---------------
module bin2bcd(data,bcd_out);
input [15:0] data;
output [11:0] bcd_out;
reg [11:0] bcd_out;
reg [13:0] temp;
reg [11:0] result;
always @(data)
 begin
 temp[13:0] = data[3:0]*625;
 result[3:0] = temp/1000;  //小数部分要乘以 0.625，这里避免浮点运算
  bcd_out[11:8]=data[11:4]/10;
  bcd_out[7:4] = data[11:4]%10;
  bcd_out[3:0] = result[3:0];
 end
endmodule

 LED数码显示部分省略。


                                      
                                          运行结果


                              I/O分配表

点击下载ds18b20.rar
              


评论
HXW718059156
高工
2012-12-18 20:20:33     打赏
38楼
LZ的作业完成得不错啊~！

评论
wenyangzeng
工程师
2012-12-18 20:55:15     打赏
39楼
版主过奖了，感觉要入门FPGA还是需要费一番功夫的，我还是菜鸟。

评论
wenyangzeng
工程师
2013-01-01 14:21:29     打赏
40楼

 2013年第一天，祝愿各位学习进步！

进程16、可逆计数器
    实验使用了3只按键，对按键过程进行了消抖处理，分别作为“清零”、“向下计数”、“向上计数”使用。使用了5位数码LED来显示双向可逆计数值，计数范围从0到99999 。该试验如果连接外部机械开关或光电开关，可以很方便的改装成生产线上实用的产品计数器。

//按键消抖：
always @ (posedge clk or negedge rst_n)
    begin
  if(!rst_n)
   begin
    key3_samp <= 1'b1;
    key2_samp <= 1'b1;
    key1_samp <= 1'b1;
   end
  else
   begin
    key3_samp <=sw3;
    key2_samp <=sw2;
    key1_samp <=sw1;
   end
 end
always @ (posedge clk or negedge rst_n)
    begin
  if(!rst_n)
   begin
    key3_samp_r <= 1'b1;
    key2_samp_r <= 1'b1;
    key1_samp_r <= 1'b1;
   end
  else
   begin
    key3_samp_r <=key3_samp;
    key2_samp_r <=key2_samp;
    key1_samp_r <=key1_samp;
   end
 end 
assign key3_sacn=key3_samp_r&(~key3_samp);
assign key2_sacn=key2_samp_r&(~key2_samp);
assign key1_sacn=key1_samp_r&(~key1_samp);

always @ (posedge clk or negedge rst_n)
    begin
  if(!rst_n)
   delay_cnt <=20'h0;
  else if(key3_scan||key2_scan||key1_scan)
   delay_cnt <=20'h0;
  else
   delay_cnt <=delay_cnt +1'b1;
 end

always @ (posedge clk or negedge rst_n)
    begin
  if(!rst_n)
   begin
    key3_rst <= 1'b1;
    key2_rst <= 1'b1;
    key1_rst <= 1'b1;
   end
  else
   if(delay_cnt==20'hfffff)
    begin
     key3_rst <=sw3;
     key2_rst <=sw2;
     key1_rst <=sw1;
    end
 end 

always @ (posedge clk or negedge rst_n)
    begin
  if(!rst_n)
   begin
    key3_rst_r <= 1'b1;
    key2_rst_r <= 1'b1;
    key1_rst_r <= 1'b1;
   end
  else
   begin
    key3_rst_r <=key3_rst;
    key2_rst_r <=key2_rst;
    key1_rst_r <=key1_rst;
   end
 end  
assign key3_low=key3_rst_r &(~key3_rst);
assign key2_low=key2_rst_r &(~key2_rst);
assign key1_low=key1_rst_r &(~key1_rst);

//计数：
always @ (posedge clk or negedge rst_n)
    begin
  if(!rst_n)
   Number <= 0;
  else
   if(key3_low)
    begin
    Number<= Number+1'b1;
    if(Number >99998)Number <=0;//加1溢出时，由于非阻塞语句，使得上下2条语句同时执行，比较值要少1
    end
   else
   if(key2_low)
    begin
     Number<= Number-1'b1;
     if(Number ==5'h20000)Number <=99999;//减1溢出时，道理同上
    end
   else
   if(key1_low)
    Number<= 0;
  end

//数码LED段码扫描：
always @(cnt_scan)
begin
   case(cnt_scan[15:13])
       3'b000 :
          DIG = 8'b1111_1110;
       3'b001 :
          DIG = 8'b0111_1111;
       3'b010 :
          DIG = 8'b1011_1111;
       3'b011 :
          DIG = 8'b1101_1111;
       3'b100 :
         DIG = 8'b1110_1111;
       3'b101 :
         DIG = 8'b1111_0111;
       3'b110 :
          DIG = 8'b1111_1011;
       3'b111 :
         DIG = 8'b1111_1101;
       default :
          DIG = 8'b1111_1110;
    endcase
end
always@(DIG)
为了大家不偷懒，就不上传完整代码了。

                               I/O分配图


                            运行结果

点击下载key_count.rar

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共45条 4/5 |‹ ‹ 1 2 3 4 5 › 跳转至页

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