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reg[1:0] state;

reg clk1;

  always@(posedge clk or negedge reset)

     if(!reset)

         state<=2'b00;

     else(state)

        2'b00:state<=2'b01;

        2'b01:state<=2'b11;

        2'b11:state<=2'b00;

        default :state<=2'b00;

  endcase

always@(negedge clk or negedge reset)

if (!reset)

clk1<=1'b0;

else 

clk1<=state[0]; //  这行和下行的代码是神马意思 

assign clk_out=state[0]&CLK1;//