EEPW论坛

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

ENTITY BirdrectionalSignal2 IS
	PORT(CLK_200M 	: IN std_logic;
             rst,re,we 	: IN std_logic;
	     data		: INOUT std_logic_vector(7 DOWNTO 0));
END BirdrectionalSignal2;

ARCHITECTURE behave OF BirdrectionalSignal2 IS
	type state_type IS(nop_state,read_state,write_state,high_z);
	SIGNAL data_in,data_out : std_logic_vector(7 DOWNTO 0);
	SIGNAL reg				: std_logic_vector(7 DOWNTO 0);
	SIGNAL present_state,next_state : state_type :=high_z;
BEGIN
	data_in<=data;--data_in accepts the data uncoditional
	
	state_transfer : PROCESS(re,we,rst)
	BEGIN
		CASE present_state  IS
			WHEN nop_state=> reg<="00000000";
				IF(re='1') THEN
					next_state<=read_state;
				ELSIF(we='1') THEN
					next_state<=write_state;
				ELSE
					next_state<=nop_state;
				END IF;
			WHEN read_state=> data<=data_out;
				IF(we='1' AND re='0') THEN
					next_state<=write_state;
				ELSIF(we='0' AND re='1') THEN
					next_state<=read_state;
				ELSIF(we='0' AND re='0') THEN
					next_state<=high_z;
				ELSE
					next_state<=nop_state;
					--data<="ZZZZZZZZ";
				END IF;
			WHEN write_state=> reg<=data_in; 
				IF(re='1' AND we='0') THEN
					next_state<=read_state;
				ELSIF(re='0' AND we='1') THEN
					next_state<=write_state;
				ELSIF(we='0' AND re='0') THEN
					next_state<=high_z;
				ElSE
					next_state<=nop_state;
				END IF;
			WHEN high_z=> data<="ZZZZZZZZ";
				IF(re='1' AND we='0') THEN
					next_state<=read_state;
				ELSIF(re='0' AND we='1') THEN
					next_state<=write_state;
				ELSIF(we='0' AND re='0') THEN
					next_state<=high_z;
				ElSE
					next_state<=nop_state;
				END IF;
		END CASE;
		IF(rst='1') THEN
			next_state<=high_z;
		END IF;
	END PROCESS state_transfer;
	
	state_register : PROCESS(CLK_200M)
	BEGIN
		IF(CLK_200M'event AND CLK_200M='1') THEN
			present_state<=next_state;
			data_out<=reg;
			--reg<=data_in;
		END IF;
	END PROCESS state_register;
	
END behave;