quartus编译产生如下警告：
 Warning (10227): Verilog HDL Port Declaration warning at SHA.v(10): data type declaration for "HASH_OUT" declares packed dimensions but the port declaration declaration does not

Warning: Found 32 output pins without output pin load capacitance assignment
Warning: Found 32 output pins without output pin load capacitance assignment
按照quartus中提供的help 给出的解决办法:
use the Assignment Editor (Assignments menu) to specify a value for the Output Pin Load logic option
结果waring还是没有消失。然后用quartus中的timequest timing analysis进行时序分析，里面显示：  
                                property                                   steup   hold
              Unconstrained Output Ports                   32        32
              Unconstrained Output Port Paths          32        32
找了很多资料还是没解决，所里写上来问问大家有没有碰到过同样的问题，帮忙解决一下。谢谢!