【应用笔记】高性能FPGA锁相环的TimeQuest时序分析(High-Performance FPGA PLL Analysis with TimeQuest)
锁相环(Phase-locked loops,PLLs)为最大化系统整个系统的性能提供了健壮的时钟管理和时钟综合能力。Altera公司的高密度Stratix器件系列提供了许多高度灵活的PLL，每个PLL都能被用户作为一个零延时缓冲器、抖动衰减器、低歪斜扇出缓冲器或者作为一个频率合成器。为了充分利用Stratix器件系列所提供的巨大功能特性，你应当对所有由Quartus II软件和TimeQuest时序分析器所产生的PLL相关报告，有一个充分的理解。
Phase-locked loops (PLLs) provide robust clock management and clock
synthesis capabilities for maximum total system performance. Altera’s
high-density Stratix device families provide many highly versatile PLLs,
and each PLL can be customized as a zero delay buffer, jitter attenuator,
low skew fan-out buffer, or as a frequency synthesizer. To take advantage
of the numerous features and capabilities provided by the Stratix device
families, you should have a full understanding of all PLL-related reports
generated by the Quartus® II software and the TimeQuest Timing
Analyzer. This application note guides you through constraining PLLs
and performing a timing analysis on the PLLs. Each of these steps
includes examples and guidelines on how to read and understand the
various reports relating to PLLs, and how to analyze and constrain PLLs
in the TimeQuest Timing Analyzer.an471.pdf