稍后传视频
代码：
module key1_9(sys_clk,
sys_rstn,
key_in,
led_out
);
input sys_clk;
input sys_rstn;
input key_in;
output [7:0] led_out;
reg [7:0] led_out;
reg [24:0] delay_cnt1;
reg [11:0] delay_cnt;
reg [1:0] delay_cnt2;
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
delay_cnt1<=25'd0;
else
begin
if(delay_cnt1==25'd39999999)
delay_cnt1<=25'd0;
else
delay_cnt1<=delay_cnt1+1'b1;
end
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
delay_cnt2<=1'd0;
else if(delay_cnt1==25'd39999999)
delay_cnt2<=1 ;
else delay_cnt2<=0;
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
delay_cnt<=25'd0;
else if(delay_cnt2==0)
delay_cnt<=delay_cnt;
else
begin
if(delay_cnt==10)
delay_cnt<=25'd0;
else
if(!key_in)
delay_cnt<=delay_cnt+1'b1;
end
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
led_out<=8'b00000000;
else if(delay_cnt==0)
led_out<=8'b00000001;
else
if(delay_cnt==1)
led_out<=8'b01001111;
else
if(delay_cnt==2)
led_out<=8'b00010010;
else
if(delay_cnt==3)
led_out<=8'b00000110;
else
if(delay_cnt==4)
led_out<=8'b01001100;
else
if(delay_cnt==5)
led_out<=8'b00100100;
else
if(delay_cnt==6)
led_out<=8'b00100000;
else
if(delay_cnt==7)
led_out<=8'b00001111;
else
if(delay_cnt==8)
led_out<=8'b00000000;
else
if(delay_cnt==9)
led_out<=8'b00000100;
end
endmodule
消抖按键控制1到9显示
代码：
module key_doudong(sys_clk,
sys_rstn,
key_in,
led_out
);
input sys_clk;
input sys_rstn;
input key_in;
output led_out;
reg [7:0] led_out;
reg [19:0] delay_cnt;
reg [4:0] delay_cnt_s;
wire key_scan;
wire key_low;
reg key_samp;
reg key_samp_r;
reg key_rst;
reg key_rst_r;
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
key_samp<=1'b1;
else
key_samp<=key_in;
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
key_samp_r<=1'b1;
else
key_samp_r<=key_in;
end
assign key_scan=key_samp_r&(~key_samp);
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
delay_cnt<=20'h0;
else if(key_scan)
delay_cnt<=20'h0;
else
delay_cnt<=delay_cnt+1'b1;
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
key_rst<=1'b1;
else if(delay_cnt==20'hfffff)
key_rst<=key_in;
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
key_rst_r<=1'b1;
else
key_rst_r<=key_rst;
end
assign key_low=key_rst_r&(~key_rst);
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
delay_cnt_s<=4'd0;
else if(delay_cnt_s==10)
delay_cnt_s<=4'd0;
else
if(key_low)
delay_cnt_s<=delay_cnt_s+1'b1;
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
led_out<=8'b00000000;
else if(delay_cnt_s==0)
led_out<=8'b00000001;
else
if(delay_cnt_s==1)
led_out<=8'b01001111;
else
if(delay_cnt_s==2)
led_out<=8'b00010010;
else
if(delay_cnt_s==3)
led_out<=8'b00000110;
else
if(delay_cnt_s==4)
led_out<=8'b01001100;
else
if(delay_cnt_s==5)
led_out<=8'b00100100;
else
if(delay_cnt_s==6)
led_out<=8'b00100000;
else
if(delay_cnt_s==7)
led_out<=8'b00001111;
else
if(delay_cnt_s==8)
led_out<=8'b00000000;
else
if(delay_cnt_s==9)
led_out<=8'b00000100;
end
endmodule
拨码开关控制八进制数码显示
代码：
module led_display_sw1_8 (sys_clk,
sys_rstn,
key_in,
sm_seg,
sm_bit
);
input sys_clk;
input sys_rstn;
output [7:0] sm_seg;
output [7:0] sm_bit;
reg [7:0] sm_seg;
reg [7:0] sm_bit;
reg [3:0] disp_dat;
input [7:0] key_in;
always@(key_in)
begin
case(key_in)
8'b11111111:disp_dat = 4'h0;
8'b11111110:disp_dat = 4'h1;
8'b11111101:disp_dat = 4'h2;
8'b11111011:disp_dat = 4'h3;
8'b11110111:disp_dat = 4'h4;
8'b11101111:disp_dat = 4'h5;
8'b11011111:disp_dat = 4'h6;
8'b10111111:disp_dat = 4'h7;
8'b01111111:disp_dat = 4'h8;
endcase
end
always@(disp_dat)
begin
case (disp_dat)
4'h0:sm_seg = 8'b11111111;
4'h1:sm_seg = 8'b11001111;
4'h2:sm_seg = 8'b10010010;
4'h3:sm_seg = 8'b10000110;
4'h4:sm_seg = 8'b11001100;
4'h5:sm_seg = 8'b10100100;
4'h6:sm_seg = 8'b10100000;
4'h7:sm_seg = 8'b10001111;
4'h8:sm_seg = 8'b10000000;
endcase
end
always@(disp_dat)
begin
case(disp_dat)
4'h1:sm_bit = 8'b11111110;
4'h2:sm_bit = 8'b11111101;
4'h3:sm_bit = 8'b11111011;
4'h4:sm_bit = 8'b11110111;
4'h5:sm_bit = 8'b11101111;
4'h6:sm_bit = 8'b11011111;
4'h7:sm_bit = 8'b10111111;
4'h8:sm_bit = 8'b01111111;
endcase
end
endmodule
60模动态显示计数器
代码：
module led_60dongtai(sys_clk,
sys_rstn,
key_in,
sm_bit,
sm_seg,
);
input sys_clk;
input sys_rstn;
input key_in;
reg [19:0] delay_cnt;
reg [19:0] delay_cnt1;
reg [7:0] led;
wire key_scan;
wire key_low;
reg key_samp;
reg key_samp_r;
reg key_rst;
reg key_rst_r;
output [7:0] sm_seg;
output [7:0] sm_bit;
reg [7:0] sm_seg;
reg [7:0] sm_bit;
reg [4:0] dataout_buf;
reg [2:0] disp_dat;
////////按键//////
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
key_samp<=1'b1;
else
key_samp<=key_in;
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
key_samp_r<=1'b1;
else
key_samp_r<=key_in;
end
assign key_scan=key_samp_r&(~key_samp);
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
delay_cnt<=20'h0;
else if(key_scan)
delay_cnt<=20'h0;
else
delay_cnt<=delay_cnt+1'b1;
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
key_rst<=1'b1;
else if(delay_cnt==20'hfffff)
key_rst<=key_in;
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
key_rst_r<=1'b1;
else
key_rst_r<=key_rst;
end
assign key_low=key_rst_r&(~key_rst);
///////计数器///////
always @(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
led<=4'b0;
else if(key_low)
begin
if(led[3:0]==9)
begin
led[3:0]<=0;
if (led[7:4]==5)
led[7:4]<=0;
else led[7:4]<=led[7:4]+1;
end
else
led[3:0]<=led[3:0]+1;
end
end
//////显示//////
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
delay_cnt1<=16'd0;
else
begin
if(delay_cnt1==16'd49999)
delay_cnt1<=16'd0;
else
delay_cnt1<=delay_cnt1+1'b1;
end
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
disp_dat<=3'd0;
else
begin
if(delay_cnt1==16'd49999)
disp_dat<=disp_dat+1'b1;
else
disp_dat<=disp_dat;
end
end
always @(disp_dat)
begin
case(disp_dat)
3'b000:
sm_bit = 8'b1111_1110;
3'b001:
sm_bit = 8'b1111_1101;
default:
sm_bit = 8'b1111_1110;
endcase
end
always@(sm_bit)
begin
case(sm_bit)
8'b1111_1110:
dataout_buf=led[7:4];
8'b1111_1101:
dataout_buf=led[3:0];
default:
dataout_buf=8;
endcase
end
always@(dataout_buf)
begin
case (dataout_buf)
4'h0:sm_seg = 8'b00000001;
4'h1:sm_seg = 8'b01001111;
4'h2:sm_seg = 8'b00010010;
4'h3:sm_seg = 8'b00000110;
4'h4:sm_seg = 8'b01001100;
4'h5:sm_seg = 8'b00100100;
4'h6:sm_seg = 8'b00100000;
4'h7:sm_seg = 8'b00001111;
4'h8:sm_seg = 8'b00000000;
4'h9:sm_seg = 8'b00000100;
4'ha:sm_seg = 8'b00001000;
4'hb:sm_seg = 8'b00000000;
4'hc:sm_seg = 8'b00110001;
4'hd:sm_seg = 8'b00000001;
4'he:sm_seg = 8'b00110000;
4'hf:sm_seg = 8'b00111000;
default:
sm_seg = 8'b00000001;
endcase
end
endmodule
近期手上没有摄像机，所以没能上传视频，过段时间再一块上传
蜂鸣器作业
警笛
参考 http://wenku.baidu.com/view/031ac2630b1c59eef8c7b432.html
代码
module jingche(sys_clk,
sys_rstn,
beep
);
input sys_clk;
input sys_rstn;
output beep;
reg beep;
reg [22:0] div_cnt;
reg [14:0] delay_cnt;
wire [14:0] delay_end;
wire [6:0] ramp;
assign ramp=(div_cnt[22]?div_cnt[21:15]:~div_cnt[21:15]);
assign delay_end={2'b01,ramp,6'b000000};
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
div_cnt<=23'd0;
else
div_cnt<=div_cnt+1'b1;
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
delay_cnt<=delay_end;
else
if(delay_cnt==15'd0)
begin
beep<=~beep;
delay_cnt<=delay_end;
end
else
delay_cnt<=delay_cnt-1'b1;
end
endmodule
蜂鸣器作业2
自动播放音乐
参考的是 http://wenku.baidu.com/view/42a39e22aaea998fcc220e7a.html
具体是什么音乐不太清楚
代码
module yinyue(sys_clk,
sys_rstn,
beep
);
input sys_clk;
input sys_rstn ;
output beep;
reg beep_r;
reg [7:0] state;
reg [15:0] count,
count_end;
reg [23:0] count1;
parameter L_5=16'd63775,
L_6=16'd56818,
M_1=16'd47773,
M_2=16'd42567,
M_3=16'd37919,
M_5=16'd31887,
M_6=16'd28409,
H_1=16'd23923;
parameter TIME=12000000;
assign beep=beep_r;
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
count<=25'd0;
else
begin
count<=count+1'b1;
if(count==count_end)
begin
count<=16'h0;
beep_r<=!beep_r;
end
end
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
count1<=25'd0;
else begin
if(count1<TIME)
count1=count1+1'b1;
else
begin
count1=24'd0;
if(state==8'd147)
state=8'd0;
else
state=state+1'b1;
case(state)
8'd0,8'd1: count_end=L_5;
8'd2,8'd3,8'd4,8'd5,8'd6,8'd7,8'd8: count_end=M_1;
8'd9,8'd10: count_end=M_3;
8'd11,8'd12,8'd13,8'd14: count_end=M_2;
8'd15: count_end=M_1;
8'd16,8'd17: count_end=M_2;
8'd18,8'd19: count_end=M_3;
8'd20,8'd21,8'd22,8'd23,8'd24: count_end=M_1;
8'd25,8'd26: count_end=M_3;
8'd27,8'd28: count_end=M_5;
8'd29,8'd30,8'd31,8'd32,8'd33: count_end=M_6;
8'd34,8'd35,8'd36,8'd37,8'd38: count_end=M_6;
8'd34,8'd35,8'd36,8'd37: count_end=M_5;
8'd34,8'd35,8'd36: count_end=M_3;
8'd46,8'd47: count_end=M_1;
8'd48,8'd49,8'd50,8'd51: count_end=M_2;
8'd52: count_end=M_1;
8'd53,8'd54: count_end=M_2;
8'd55,8'd56: count_end=M_3;
8'd57,8'd58,8'd59,8'd60: count_end=M_1;
8'd61,8'd62,8'd63: count_end=M_6;
8'd64,8'd65: count_end=M_5;
8'd66,8'd67,8'd68,8'd69: count_end=M_1;
8'd70,8'd71,8'd72,8'd73: count_end=M_1;
8'd74,8'd75: count_end=M_6;
8'd76,8'd77,8'd78,8'd79: count_end=M_5;
8'd80,8'd81,8'd82: count_end=M_3;
8'd83,8'd84: count_end=M_1;
8'd85,8'd86,8'd87,8'd88: count_end=M_2;
8'd89: count_end=M_1;
8'd90,8'd91: count_end=M_2;
8'd92,8'd93: count_end=M_6;
8'd94,8'd95,8'd96,8'd97: count_end=M_5;
8'd98,8'd99,8'd100: count_end=M_3;
8'd101,8'd102: count_end=M_5;
8'd103,8'd104,8'd105,8'd106: count_end=M_6;
8'd107,8'd108,8'd109,8'd110: count_end=M_6;
8'd111,8'd112: count_end=H_1;
8'd113,8'd114,8'd115,8'd116: count_end=M_5;
8'd117,8'd118,8'd119: count_end=M_3;
8'd120,8'd121: count_end=M_6;
8'd122,8'd123,8'd124,8'd125: count_end=M_2;
8'd126: count_end=M_1;
8'd127,8'd128: count_end=M_2;
8'd129,8'd130: count_end=M_3;
8'd131,8'd132,8'd133,8'd134: count_end=M_1;
8'd135,8'd136,8'd137: count_end=L_6;
8'd138,8'd139: count_end=M_5;
8'd140,8'd141,8'd142,8'd143: count_end=M_1;
8'd144,8'd145,8'd146,8'd147: count_end=M_1;
default:count_end=16'hffff;
endcase
end
end
end
endmodule
液晶屏作业显示其他字符
只是把原程序改动了一下显示
“xiaohe eepw FPGA DIY！！！”
代码
`timescale 1ns / 1ps
module lcd1602(sys_clk ,
sys_rstn ,
lcd_rs ,
lcd_rw ,
lcd_en ,
lcd_data
);
//输入输出信号定义
input sys_clk ;//系统时钟输入
input sys_rstn ;//系统复位信号，低电平有效
output lcd_rs ;//lcd的寄存器选择输出信号
output lcd_rw ;//lcd的读、写操作选择输出信号
output lcd_en ;//lcd使能信号
output [7:0] lcd_data ;//lcd的数据总线（不进行读操作，故为输出）
//寄存器定义
reg lcd_rs ;
reg clk_div ;
reg [17:0] delay_cnt ;
reg [7:0] lcd_data ;
reg [4:0] char_cnt ;
reg [7:0] data_disp ;
reg [9:0] state ;
parameter idle = 10'b000000000, //初始状态，下一个状态为CLEAR
clear = 10'b000000001, //清屏
set_function = 10'b000000010, //功能设置：8位数据接口/2行显示/5*8点阵字符
switch_mode = 10'b000000100, //显示开关控制：开显示，光标和闪烁关闭
set_mode = 10'b000001000, //输入方式设置：数据读写操作后，地址自动加一/画面不动
shift = 10'b000010000, //光标、画面位移设置：光标向左平移一个字符位（光标显示是关闭的，所以实际上设置是看不出效果的）
set_ddram1 = 10'b000100000, //设置DDRAM的地址：第一行起始为0x00（注意输出时DB7一定要为1）
set_ddram2 = 10'b001000000, //设置DDRAM的地址：第二行为0x40（注意输出时DB7一定要为1）
write_ram1 = 10'b010000000, //数据写入DDRAM相应的地址
write_ram2 = 10'b100000000; //数据写入DDRAM相应的地址
assign lcd_rw = 1'b0; //没有读操作，R/W信号始终为低电平
assign lcd_en = clk_div; //E信号出现高电平以及下降沿的时刻与LCD时钟相同
//时钟分频
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
begin
delay_cnt<=18'd0;
clk_div<=1'b0;
end
else if(delay_cnt==18'd249999)
begin
delay_cnt<=18'd0;
clk_div<=~clk_div;
end
else
begin
delay_cnt<=delay_cnt+1'b1;
clk_div<=clk_div;
end
end
always@(posedge clk_div or negedge sys_rstn) //State Machine
begin
if(!sys_rstn)
begin
state <= idle;
lcd_data <= 8'bzzzzzzzz;
char_cnt <= 5'd0;
end
else
begin
case(state)
idle: begin //初始状态
state <= clear;
lcd_data <= 8'bzzzzzzzz;
end
clear: begin //清屏
state <= set_function;
lcd_rs<=1'b0;
lcd_data <= 8'b00000001;
end
set_function: //功能设置(38H)：8位数据接口/2行显示/5*8点阵字符
begin
state <= switch_mode;
lcd_rs<=1'b0;
lcd_data <= 8'b00111000;
end
switch_mode: //显示开关控制(0CH)：开显示，光标和闪烁关闭
begin
state <= set_mode;
lcd_rs<=1'b0;
lcd_data <= 8'b00001100;
end
set_mode:begin //输入方式设置(06H)：数据读写操作后，地址自动加一/画面不动
state <= shift;
lcd_rs<=1'b0;
lcd_data <= 8'b00000110;
end
shift: begin //光标、画面位移设置(10H)：光标向左平移一个字符位（光标显示是关闭的，所以实际上设置是看不出效果的）
state <= set_ddram1;
lcd_rs<=1'b0;
lcd_data <= 8'b0001_0000;
end
set_ddram1: //设置DDRAM的地址：第一行起始为00H（注意输出时DB7一定要为1）
begin
state <= write_ram1;
lcd_rs<=1'b0;
lcd_data <= 8'b1000_0000;//Line1
end
set_ddram2: //设置DDRAM的地址：第二行为40H（注意输出时DB7一定要为1）
begin
state <= write_ram2;
lcd_rs<=1'b0;
lcd_data <= 8'b1100_0000;//Line2
end
write_ram1:
begin
if(char_cnt <=5'd10)
begin
char_cnt <= char_cnt + 1'b1;
lcd_rs<=1'b1;
lcd_data <= data_disp;
state <= write_ram1;
end
else
begin
state <= set_ddram2;
end
end
write_ram2:
begin
if(char_cnt <=5'd26)
begin
char_cnt <= char_cnt + 1'b1;
lcd_rs<=1'b1;
lcd_data <= data_disp;
state <= write_ram2;
end
else
begin
char_cnt <=5'd0;
state <= shift;
end
end
default: state <= idle;
endcase
end
end
always @(char_cnt) //输出的字符
begin
case (char_cnt)
5'd0: data_disp = "x";
5'd1: data_disp = "i";
5'd2: data_disp = "a";
5'd3: data_disp = "o";
5'd4: data_disp = " ";
5'd5: data_disp = "h";
5'd6: data_disp = "e";
5'd7: data_disp = " ";
5'd8: data_disp = " ";
5'd9: data_disp = " ";
5'd10: data_disp = " ";
5'd11: data_disp = "e";
5'd12: data_disp = "e";
5'd13: data_disp = "p";
5'd14: data_disp = "w";
5'd15: data_disp = " ";
5'd16: data_disp = "F";
5'd17: data_disp = "P";
5'd18: data_disp = "G";
5'd19: data_disp = "A";
5'd20: data_disp = " ";
5'd21: data_disp = "D";
5'd22: data_disp = "I";
5'd23: data_disp = "Y";
5'd24: data_disp = "!";
5'd25: data_disp = "!";
5'd26: data_disp = "!";
default : data_disp ="";
endcase
end
endmodule
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