请师兄师弟们上传用FPGA产生PWM信号控制LED明暗的例程，最好加上注析，不胜感激....
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module Led( clk, rst_n, out );
input clk, rst_n;
output out;
reg[5:0] out;
reg[15:0] count, pwm; //周期,脉宽
// PWM周期数累加
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin count <= 16'h0; end
else
begin count <= count + 1'b1; end
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin out <= 6'h3f; end
else
begin
if(count[15] == 1) //周期数清0
count <= 16'h0;
else
begin
if(count < pwm)
out <= 6'h3f;
else
out <= 6'h00;
end
end
end
always @(posedge count[14] or rst_n)
begin
if(!rst_n)
begin pwm <= 16'h0; end
else
begin
pwm <= pwm + 1'b1;
if(pwm[13] == 1)
begin
pwm <= 16'h0;
end
end
end
endmodule
module Led( clk, rst_n, out );
input clk, rst_n;
output out;
reg[5:0] out;
reg[15:0] count, pwm; //周期,脉宽
// PWM周期数累加
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin count <= 16'h0; end
else
begin count <= count + 1'b1; end
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin out <= 6'h3f; end
else
begin
if(count[15] == 1) //周期数清0
count <= 16'h0;
else
begin
if(count < pwm)
out <= 6'h3f;
else
out <= 6'h00;
end
end
end
always @(posedge count[14] or rst_n)
begin
if(!rst_n)
begin pwm <= 16'h0; end
else
begin
pwm <= pwm + 1'b1;
if(pwm[13] == 1)
begin
pwm <= 16'h0;
end
end
end
endmodule
无法编译,或有没有更好的例程,谢谢...
共8条
1/1 1 跳转至页
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