-------------------------------------------------------------------------------- 4.0 ISA Bus Timing Diagrams 8-Bit I/O Bus Cycles ________ BALE __| |_________________________________________ _ ______________________________________________ __ SA(15:0) _><______________________________________________><__ -SBHE ______________ _______ -IOR/W |______________________________| _____________ SD(7:0) -------------------------------------<_____________>- (READ) __________________________________ SD(7:0) ----------------<__________________________________>- (WRITE) __________________ _ _ _ _ _ _ _ _ _ _ _ _ _________ I/OCHRDY |________________________| 8-Bit Memory Bus Cycles _____ BALE ________| |______________________________________ _ ________________ ________________________________ LA(23:17) _><________________><________________________________ _______ ________________________________________ __ SA(19:0) _______><________________________________________><__ ______________ _______ -MEMR/W |______________________________| _____________ SD(7:0) -------------------------------------<_____________>- (READ) __________________________________ SD(7:0) ----------------<__________________________________>- (WRITE) __________________ _ _ _ _ _ _ _ _ _ _ _ _ _________ I/OCHRDY |________________________| 16-Bit I/O Bus Cycles ________ BALE ______________| |_____________________________ _____________ __________________________________ __ SA(15:0) _____________><__________________________________><__ _________________ ___ -IOCS16 |_______________________________| _____________________ ______ -IOR/W |________________________| __________________ SD(15:0) -----------------------------<__________________>---- (READ) ________________________ SD(15:0) -----------------------<________________________>---- (WRITE) _______________________ _ _ _ _ _ _ _ _ _ _ ______ I/OCHRDY |___________________| 16-Bit Memory Bus Cycles (1 or more Wait States) ______ BALE _________________| |____________________________ ___ ________________________ ______________________ LA(23:17) ___><________________________><______________________ ________________ ________________________________ _ SA(19:0) ________________><________________________________><_ _______ ______________________ -MEMCS16 |______________________| ________________________ ______ -MEMR/W |_____________________| _______________ SD(15:0) --------------------------------<_______________>---- (READ) _____________________ SD(15:0) --------------------------<_____________________>---- (WRITE) __________________________ _ _ _ _ _ _ _ _ __________ I/OCHRDY |_______________| 16-Bit Memory Bus Cycles (0 Wait State) ______ BALE _________________| |____________________________ ___ ________________________ ______________________ LA(23:17) ___><________________________><______________________ ________________ _________________________ ________ SA(19:0) ________________><_________________________><________ _______ ______________________ -MEMCS16 |______________________| _________________________ ______________________ -0WS |____| ________________________ ________________ -MEMR/W |___________| ______ SD(15:0) --------------------------------<______>------------- (READ) ____________ SD(15:0) --------------------------<____________>------------- (WRITE) DMA Read ______________ DRQ(n) __| |___________________________________ _______________ __________ -DACK(n) |__________________________| ____________________________________ AEN,BALE ________| |_______ _______________ ___________________________ _______ SA(15:0) _______________><___________________________><_______ -SBHE ________________ ________________________ _________ SA(19:16) ________________><________________________><_________ LA(23:17) ____________________ __________ -MEMR |_____________________| ____________ SD(15:0) -------------------------------<____________>-------- ______________________ ___________ -IOW |__________________| __________ TC _______________________________| |__________ ________________________ _____________________ I/OCHRDY |______| DMA Write ______________ DRQ(n) __| |___________________________________ _______________ __________ -DACK(n) |__________________________| ____________________________________ AEN,BALE ________| |_______ _______________ ___________________________ _______ SA(15:0) _______________><___________________________><_______ -SBHE ________________ ________________________ _________ SA(19:16) ________________><________________________><_________ LA(23:17) ____________________ __________ -IOR |_____________________| ____________ SD(15:0) -------------------------------<____________>-------- ______________________ ___________ -MEMW |__________________| __________ TC _______________________________| |__________ ________________________ _____________________ I/OCHRDY |______| Alternate Bus Master Cycles ___________________________________ DRQ(n) __| |______________ _______________ __________ -DACK(n) |__________________________| __________________ _______ -MASTER |__________________________| __________________ _______ AEN ________| |__________________________| |_ _____________________________________________________ BALE ________| |_ ________________________ ___________ ______________ SA(19:0) ________________________><___________><_______________ -SBHE ________________________ ___________ ______________ LA(23:17) ________________________><___________><______________ _____________________________ _________________ -IOR,-IOW |_____| -MEMR,-MEMW _____ SD(15:0) -------------------------------<_____>--------------- Memory Refresh Cycles _______________ _______________ -REFRESH |_____________________| _________________ ____________ ____________________ SA(9:0) _________________><____________><____________________ ______________________ ________________ -SMEMR |_____________| _________________________ _ _ _ _ ___________________ I/OCHRDY |_______| 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