【应用手册】AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
This application note shows how you can leverage the verification environment in the
testbench provided in the Altera® Triple Speed Ethernet MegaCore® function to debug
your system design. You can use the different types of loopback in the testbench to
simulate your system design, and create various common scenarios by configuring
the parameters and the state machine in the testbench.
The Triple Speed Ethernet MegaCore function consists of a 10/100/1000 Mbps
Ethernet media access controller (MAC), a 1000BASE-X physical coding sub-layer
(PCS), and an optional physical medium attachment (PMA). The Triple Speed
Ethernet MegaCore function supports seamless interface to commercial Ethernet PHY
devices via medium independent interface (MII) and gigabit medium independent
interface (GMII). The MegaCore function also supports reduced gigabit medium
independent interface (RGMII) in 10/100/1000 Mbps.
The Triple Speed Ethernet MegaCore function provides a testbench that supports
simulation of all basic Ethernet packet transactions, and has an easy-to-use simulation
environment for any standard HDL simulator. The testbench consists of device under
test (DUT) modules which are the custom MegaCore function variations, the Ethernet
frame generators, and clock and reset generators.
The testbench is intended for simulating common configurations and may not cover
all the possible configurations of the Triple Speed Ethernet MegaCore function.
an585.pdf