【应用手册】AN 588: 10-Gbps Ethernet Hardware Demonstration Reference Designs
The reference designs demonstrate wire-speed operation of the Altera® 10-Gbps Ethernet
(10GbE) reference design component described in AN516: 10-Gbps Ethernet Reference Design;
one using Arria® II GX devices and the other using Stratix® IV GX devices. The reference
designs are SOPC Builder systems that include one instance of a custom 10GbE component
configured as a media access control (MAC) with a XAUI transceiver.
The designs provide a flexible test and demonstration platform on which you can control,
test, and monitor 10GbE operations in different loopback options. You can use the reference
designs in a stand-alone configuration or in a multi-equipment configuration with an
external 10-Gbps Ethernet legacy system or standard test equipment.
The 10GbE hardware demonstration reference design has the following features:
■ Stand-alone and easy-to-use reference design example with flexibility to support twosystem
interoperability in various configurations.
■ Requires minimal hardware.
■ Supports 10GbE operations in XAUI mode.
■ Supports programmable settings for number of packets, packet length, and payload-data
type.
■ Demonstrates transmission and reception of Ethernet packets at the maximum theoretical
data rates without errors, through external loopback, internal loopback, or both types of
loopback path.
■ Supports different loopback mechanisms including external loopback through a CX4
loopback device, external loopback through X2 modules with a loopback optical cable
assembly, external loopback through an Altera high-speed mezzanine connector (HSMC)
loopback board, internal physical medium attachment (PMA) loopback, and internal
MAC loopback.
■ Includes support for gathering throughput statistics.
■ Provides custom command-line interface (CLI) commands to control the design, monitor
transmitted and received packets, and generate and display statistics information from
within the Nios II IDE.an588.pdf