The Virtex® FPGA series provides dedicated on-chip blocks of 4096 bit dual-port synchronous RAM, which are ideal for use in FIFO applications. This application note describes a way to create a common-clock (synchronous) version and an independent-clock (asynchronous) version of a 511 x 8 FIFO, with the depth and width being adjustable within the Verilog or VHDL code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. This document is obsolete/under obsolescence.

xapp131.pdf