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【应用笔记】在Stratix和Stratix GX器件中实现PLL重配置(Implementing PLL Reconfiguration in Stratix &Stratix GX Devices)
锁相环(Phase-locked loops,PLLs)使用几个分频计数器和延时单元，来实现频率综合和相移。
Phase-locked loops (PLLs) use several divide counters and delay
elements to perform frequency synthesis and phase shifts. In StratixTM
and Stratix GX enhanced PLLs, these counters and delay elements are
configurable in real-time. Designers can vary output clock frequency and
time delay in real time without reconfiguring the entire FPGA.an282.pdf