module miaobiao(
clk,
rst,
led0,led1,led2,led3,led4,led5,led6,led7,
led_r,led_g,led_y,
seg,dig
);
input clk;
input rst;
output led0,led1,led2,led3,led4,led5,led6,led7;
output led_r,led_g,led_y;
output[7:0] seg;
output[7:0] dig;
reg[7:0] seg_reg;
reg[7:0] dig_reg;
reg[7:0] seg_reg0;
reg[7:0] seg_reg1;
reg[7:0] seg_reg2;
reg[7:0] seg_reg3;
reg[7:0] seg_reg4;
reg[7:0] seg_reg5;
reg[3:0] sum,sum1,sum2,sum3,sum4,sum5;
reg[31:0] count;
reg[10:0] led_out;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
count<=31'd0;
sum<=4'b0; sum1<=4'b0; sum2<=4'b0; sum3<=4'b0; sum4<=4'b0; sum5<=4'b0;
end
else
begin
if(count==31'd1_000_000)
begin
count<=31'd0;
sum<=sum+1'b1;
if(sum==4'h9)
begin
sum1<=sum1+1'b1; sum<=4'b0;
if(sum1==4'h5)
begin
sum2<=sum2+1'b1; sum1<=4'b0;
if(sum2==4'h9)
begin
sum3<=sum3+1'b1; sum2<=4'b0;
if(sum3==4'h5)
begin
sum4<=sum4+1'b1; sum3<=4'b0;
if(sum4==4'h9)
begin
sum5<=sum5+1'b1; sum4<=4'b0;
end
end
end
end
end
end
else
begin
count<=count+1'b1;
end
end
end
always @(posedge clk or negedge rst)
begin
if(!rst)
led_out <= 1'b0;
else
if(count >= 31'd0 && count < 31'd20_000_000)
led_out <= 11'b111_1111_1110;
else if(count >= 31'd20_000_000 && count < 31'd40_000_000)
led_out <= 11'b111_1111_1101;
else if(count >= 31'd40_000_000 && count < 31'd60_000_000)
led_out <= 11'b111_1111_1011;
else if(count >= 31'd60_000_000 && count < 31'd80_000_000)
led_out <= 11'b111_1111_0111;
else if(count >= 31'd80_000_000 && count < 31'd100_000_000)
led_out <= 11'b111_1110_1111;
else if(count >= 31'd100_000_000 && count < 31'd120_000_000)
led_out <= 11'b111_1101_1111;
else if(count >= 31'd120_000_000 && count < 31'd140_000_000)
led_out <= 11'b111_1011_1111;
else if(count >= 31'd140_000_000 && count < 31'd160_000_000)
led_out <= 11'b111_0111_1111;
else if(count >= 31'd160_000_000 && count < 31'd180_000_000)
led_out <= 11'b110_1111_1111;
else if(count >= 31'd180_000_000 && count < 31'd200_000_000)
led_out <= 11'b101_1111_1111;
end
///////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
seg_reg0<=8'b0000_0000;
end
else
begin
case(sum)
4'h0: seg_reg0<=8'b1100_0000; //0
4'h1: seg_reg0<=8'b1111_1001; //1
4'h2: seg_reg0<=8'b1010_0100; //2
4'h3: seg_reg0<=8'b1011_0000; //3
4'h4: seg_reg0<=8'b1001_1001; //4
4'h5: seg_reg0<=8'b1001_0010; //5
4'h6: seg_reg0<=8'b1000_0010; //6
4'h7: seg_reg0<=8'b1111_1000; //7
4'h8: seg_reg0<=8'b1000_0000; //8
4'h9: seg_reg0<=8'b1001_0000; //9
default seg_reg0<=8'b1100_0000;
endcase
end
end
/////////////////////////////////////////////////////////////////////////////
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
seg_reg1<=8'b0000_0000;
end
else
begin
case(sum1)
4'h0: seg_reg1<=8'b1100_0000; //0
4'h1: seg_reg1<=8'b1111_1001; //1
4'h2: seg_reg1<=8'b1010_0100; //2
4'h3: seg_reg1<=8'b1011_0000; //3
4'h4: seg_reg1<=8'b1001_1001; //4
4'h5: seg_reg1<=8'b1001_0010; //5
4'h6: seg_reg1<=8'b1000_0010; //6
4'h7: seg_reg1<=8'b1111_1000; //7
4'h8: seg_reg1<=8'b1000_0000; //8
4'h9: seg_reg1<=8'b1001_0000; //9
default seg_reg1<=8'b1100_0000;
endcase
end
end
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
seg_reg2<=8'b0000_0000;
end
else
begin
case(sum2)
4'h0: seg_reg2<=8'b1100_0000; //0
4'h1: seg_reg2<=8'b1111_1001; //1
4'h2: seg_reg2<=8'b1010_0100; //2
4'h3: seg_reg2<=8'b1011_0000; //3
4'h4: seg_reg2<=8'b1001_1001; //4
4'h5: seg_reg2<=8'b1001_0010; //5
4'h6: seg_reg2<=8'b1000_0010; //6
4'h7: seg_reg2<=8'b1111_1000; //7
4'h8: seg_reg2<=8'b1000_0000; //8
4'h9: seg_reg2<=8'b1001_0000; //9
default seg_reg2<=8'b1100_0000;
endcase
end
end
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
seg_reg3<=8'b0000_0000;
end
else
begin
case(sum3)
4'h0: seg_reg3<=8'b1100_0000; //0
4'h1: seg_reg3<=8'b1111_1001; //1
4'h2: seg_reg3<=8'b1010_0100; //2
4'h3: seg_reg3<=8'b1011_0000; //3
4'h4: seg_reg3<=8'b1001_1001; //4
4'h5: seg_reg3<=8'b1001_0010; //5
4'h6: seg_reg3<=8'b1000_0010; //6
4'h7: seg_reg3<=8'b1111_1000; //7
4'h8: seg_reg3<=8'b1000_0000; //8
4'h9: seg_reg3<=8'b1001_0000; //9
default seg_reg3<=8'b1100_0000;
endcase
end
end
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
seg_reg4<=8'b0000_0000;
end
else
begin
case(sum4)
4'h0: seg_reg4<=8'b1100_0000; //0
4'h1: seg_reg4<=8'b1111_1001; //1
4'h2: seg_reg4<=8'b1010_0100; //2
4'h3: seg_reg4<=8'b1011_0000; //3
4'h4: seg_reg4<=8'b1001_1001; //4
4'h5: seg_reg4<=8'b1001_0010; //5
4'h6: seg_reg4<=8'b1000_0010; //6
4'h7: seg_reg4<=8'b1111_1000; //7
4'h8: seg_reg4<=8'b1000_0000; //8
4'h9: seg_reg4<=8'b1001_0000; //9
default seg_reg4<=8'b1100_0000;
endcase
end
end
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
seg_reg5<=8'b0000_0000;
end
else
begin
case(sum5)
4'h0: seg_reg5<=8'b1100_0000; //0
4'h1: seg_reg5<=8'b1111_1001; //1
4'h2: seg_reg5<=8'b1010_0100; //2
4'h3: seg_reg5<=8'b1011_0000; //3
4'h4: seg_reg5<=8'b1001_1001; //4
4'h5: seg_reg5<=8'b1001_0010; //5
4'h6: seg_reg5<=8'b1000_0010; //6
4'h7: seg_reg5<=8'b1111_1000; //7
4'h8: seg_reg5<=8'b1000_0000; //8
4'h9: seg_reg5<=8'b1001_0000; //9
default seg_reg5<=8'b1100_0000;
endcase
end
end
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk or negedge rst)
begin
case(count[15:13])
3'h0: dig_reg <= 8'b1111_1110; //seg_reg<=seg_reg0;
3'h1: dig_reg <= 8'b1111_1101;
3'h2: dig_reg <= 8'b1111_1011;
3'h3: dig_reg <= 8'b1111_0111;
3'h4: dig_reg <= 8'b1110_1111;
3'h5: dig_reg <= 8'b1101_1111;
3'h6: dig_reg <= 8'b1011_1111;
3'h7: dig_reg <= 8'b0111_1111;
default dig_reg <= 8'b1111_1111;
endcase
end
always @(dig_reg)
begin
case(dig_reg)
8'b1111_1110: seg_reg <= seg_reg0; //seg_reg<=seg_reg0;
8'b1111_1101: seg_reg <= seg_reg1;
8'b1111_1011: seg_reg <= 8'b1011_1111;
8'b1111_0111: seg_reg <= seg_reg2;
8'b1110_1111: seg_reg <= seg_reg3;
8'b1101_1111: seg_reg <= 8'b1011_1111;
8'b1011_1111: seg_reg <= seg_reg4;
8'b0111_1111: seg_reg <= seg_reg5;
default seg_reg <= seg_reg0;
endcase
end
assign led0 =led_out[0];
assign led1 =led_out[1];
assign led2 =led_out[2];
assign led3 =led_out[3];
assign led4 =led_out[4];
assign led5 =led_out[5];
assign led6 =led_out[6];
assign led7 =led_out[7];
assign led_r = led_out[8];
assign led_g = led_out[9];
assign led_y = led_out[10];
assign seg = seg_reg;
assign dig = dig_reg;
endmodule
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