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hellok FPGA DIY进程贴

hellok

工程师

2012-10-15 22:21:26 打赏

只看楼主 1楼

收到东西有几天了，一直比较忙，没怎么整，今天总算焊完了，下载了测试程序进去，提示下载成功，可居然没跑起来，LED一个也不亮，不知道怎么回事,要再找时间查查

10-20 焊得有些问题，先用着吧。点亮了下LED，拍个照看不到效果，就不上图了，简单的很的LED闪烁没什么看的，在7楼
10-24 太慢了，还是闪灯的，跑马灯+流水灯+闪两次，在8楼，就不上图了
11-26 都一个月没更新了，自己都差多不忘了这事。。。。弄了下数码管的显示。
11-28按键控制数码管显示
11-29蜂鸣器

关键词： hellok 进程

hellok

工程师

2012-10-16 08:32:39 打赏

2楼

是你的程序，也是焊的Y2，后来发现刚下载完后工作正常，断电后再上电就不工作了，再重新下载后又工作。本来以为是复位部分的问题，可检查了没发现有什么不正常。

hellok

工程师

2012-10-16 18:08:24 打赏

3楼

有可能，烙铁有问题，加热到一定程度烙铁上就有比较高的电压，居然把自己电了一下。。。。。。不过刚下载完能工作至少说明没彻底烧掉

hellok

工程师

2012-10-20 13:40:12 打赏

4楼

//*********************************************************
//文件名称： led.v
//说明： LED闪烁
//版本号： V0.0 2012.10.19
//*********************************************************

module led (led,clk_50M,rst_n);
output[10:0] led;
input clk_50M;
input rst_n;
reg[10:0] mled;
reg[23:0] cnt;

always @(posedge clk_50M, negedge rst_n)
begin
    if (!rst_n)
        mled <= 11'b01010101010;
    else
    begin
      cnt <= cnt + 1;
    if (cnt == 23'd2500000)
            mled <= ~mled;
    end
end

assign led = mled;
endmodule

hellok

工程师

2012-10-24 23:56:21 打赏

5楼

//*********************************************************
//文件名称： huayang.v
//说明：手把手教你学习FPGA—LED篇实验五？
//版本号： V0.0 2012.10.24
//*********************************************************

module huayang (clk, rst_n, led);
input clk, rst_n;
output [10:0] led;

reg [10:0] mled;
reg [24:0] delay_cnt;
reg [1:0] state;
reg [1:0] shs_cnt;

always @ (posedge clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= 25'd0;
else
      begin
        if (delay_cnt == 25'd24999999)
        delay_cnt <= 25'd0;
    else
        delay_cnt <= delay_cnt + 1'd1;
    end
end

always @ (posedge clk or negedge rst_n)
begin
    if (!rst_n)
      begin
      mled <= 11'b111_1111_1110;
    state <= 2'd0;
    shs_cnt <= 2'd0;
    end
else
      begin
    if (delay_cnt == 25'd24999999)
        begin
          case (state)
              2'd0:                             //跑马灯
            begin
            mled <= {mled[9:0], led[10]};
        if ( mled == 11'b011_1111_1111)
            begin
            mled <= 11'b111_1111_1111;
                  state <= 2'd1;
            end
          end
          2'd1:                             //流水灯
            begin
            mled <= mled << 1;
        if (mled == 11'b000_0000_0000)
            begin
                  mled <= 11'b111_1111_1111;
          state <= 2'd2;
            end
          end
      2'd2:                            //流水灯从右到左
            begin
            mled <= mled >> 1;
        if (mled == 11'b000_0000_0000)
            begin
                  mled <= 11'b111_1111_1111;
          state <= 2'd3;
            end
          end
        2'd3:                             //闪烁灯
            begin
            mled <= ~mled;
        shs_cnt <= shs_cnt + 1'd1;
        if (shs_cnt == 2'd3)
            begin
              shs_cnt <= 1'd0;
            mled <= 11'b111_1111_1110;
            state <= 2'd0;
          end
          end
        default:
            mled <= 11'b010_1100_1100;
          endcase
        end
    end
end

assign led = mled;

endmodule

hellok

工程师

2012-11-26 23:06:30 打赏

6楼

//*********************************************************
//文件名称： seg_sta.v
//说明：      手把手教你学习FPGA—数码管篇实验一数码管静态显示
//           拨动拨码开关控制数码管显示
//版本号：    V0.0 2012.11.20
//*********************************************************

module seg_sta (sys_clk, rst_n, led_seg, led_bit, sw_dip);

input sys_clk, rst_n;
input [7:0] sw_dip;
output [7:0] led_seg;
output [7:0] led_bit;

reg [7:0] sw_buf;
reg [7:0] led_seg;
wire [7:0] led_bit;
//reg [3:0] disp_dat; //显示数据寄存器;
reg [25:0] delay_cnt;

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= 26'd0;
else
      begin
    if (delay_cnt == 26'd49999999)
        delay_cnt <= 26'd0;
    else
        delay_cnt <= delay_cnt + 1'b1;
      end
end

/*always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      disp_dat <= 4'd0;
else
      begin
    if (delay_cnt == 26'd49999999)
        disp_dat <= disp_dat + 1'b1;
    else
        disp_dat <= disp_dat;
    end
end*/

always @ (sw_dip)
begin
    sw_buf = sw_dip;
    case (sw_buf)
      8'b11111110: led_seg = 8'hf9;
        8'b11111101: led_seg = 8'ha4;
        8'b11111011: led_seg = 8'hb0;
        8'b11110111: led_seg = 8'h99;
        8'b11101111: led_seg = 8'h92;
        8'b11011111: led_seg = 8'h82;
        8'b10111111: led_seg = 8'hf8;
        8'b01111111: led_seg = 8'h80;
        default:     led_seg = 8'h86;
endcase
end

/*always @ (disp_dat)
begin
    case (disp_dat)
      4'h0 : led_seg = 8'hc0;
    4'h1 : led_seg = 8'hf9;
    4'h2 : led_seg = 8'ha4;
    4'h3 : led_seg = 8'hb0;
    4'h4 : led_seg = 8'h99;
    4'h5 : led_seg = 8'h92;
    4'h6 : led_seg = 8'h82;
    4'h7 : led_seg = 8'hf8;
    4'h8 : led_seg = 8'h80;
    4'h9 : led_seg = 8'h90;
    4'ha : led_seg = 8'h88;
    4'hb : led_seg = 8'h83;
    4'hc : led_seg = 8'hc6;
    4'hd : led_seg = 8'ha1;
    4'he : led_seg = 8'h86;
    4'hf : led_seg = 8'h8e;
endcase
end*/

assign led_bit = 8'b00000000;

endmodule

hellok

工程师

2012-11-26 23:07:26 打赏

7楼

//*********************************************************
//文件名称： shansh.v
//说明：      手把手教你学习FPGA—数码管篇实验二数码管动态显示
//           数码管动态显示0-7例程，直接在上面更改增加模60计数功能
//版本号：    V0.0 2012.11.26
//*********************************************************

module seg_dyn (sys_clk, rst_n, led_seg, led_bit);

input sys_clk;
input rst_n;
output [7:0] led_seg;
output [7:0] led_bit;

reg [7:0] led_seg;
reg [7:0] led_bit;
reg [4:0] dataout_buf;
reg [2:0] disp_dat;
reg [15:0] delay_cnt;
reg [25:0] delay_1s;
reg [5:0] count60;
reg [3:0] count60_ge, count60_shi;

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= 16'd0;
else
      begin
    if (delay_cnt == 16'd49999)
        delay_cnt <= 16'd0;
    else
        delay_cnt <= delay_cnt + 1'b1;
    end
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      disp_dat <= 4'd0;
else
      begin
    if (delay_cnt == 16'd49999)
        disp_dat <= disp_dat + 1'b1;
    else
        disp_dat <= disp_dat;
    end
end

always @ (posedge sys_clk or negedge rst_n)   //1秒计数
begin
    if (!rst_n)
      delay_1s <= 26'd0;
else
      begin
    if (delay_1s == 26'd49999999)
        delay_1s <= 26'd0;
    else
        delay_1s <= delay_1s + 1'b1;
    end
end

always @ (posedge sys_clk or negedge rst_n)   //模60计数；
begin
    if (!rst_n)
      count60 <= 6'd0;
else
      begin
    if (count60 == 6'd60)
        count60 <= 0;
    else
        begin
    if (delay_1s == 26'd49999999)
        count60 <= count60 + 1'b1;
    else
        count60 <= count60;
    end
    end
end

always @ (disp_dat)
begin
    case (disp_dat)
      3'b000:    led_bit = 8'b1111_1110;
    3'b001:    led_bit = 8'b1111_1101;
    3'b010:    led_bit = 8'b1111_1011;
    3'b011:    led_bit = 8'b1111_0111;
    3'b100:    led_bit = 8'b1110_1111;
    3'b101:    led_bit = 8'b1101_1111;
    3'b110:    led_bit = 8'b1011_1111;
    3'b111:    led_bit = 8'b0111_1111;
    default:   led_bit = 8'b1111_1110;
endcase
end

always @ (led_bit)
begin
    count60_ge <= count60 % 10;
count60_shi <= count60 / 10;
    case (led_bit)
      8'b1111_1110:    dataout_buf = count60_ge;//0;    //模60计数的个位；
    8'b1111_1101:    dataout_buf = count60_shi;//1;
    8'b1111_1011:    dataout_buf = 2;
    8'b1111_0111:    dataout_buf = 3;
    8'b1110_1111:    dataout_buf = 4;
    8'b1101_1111:    dataout_buf = 5;
    8'b1011_1111:    dataout_buf = 6;
    8'b0111_1111:    dataout_buf = 7;
    default:         dataout_buf = 8;
endcase
end

always @ (dataout_buf)
begin
    case (dataout_buf)
      4'h0:    led_seg = 8'hc0;
    4'h1:    led_seg = 8'hf9;
    4'h2:    led_seg = 8'ha4;
    4'h3:    led_seg = 8'hb0;
    4'h4:    led_seg = 8'h99;
    4'h5:    led_seg = 8'h92;
    4'h6:    led_seg = 8'h82;
    4'h7:    led_seg = 8'hf8;
    4'h8:    led_seg = 8'h80;
    4'h9:    led_seg = 8'h90;
    4'ha:    led_seg = 8'h88;
    4'hb:    led_seg = 8'h83;
    4'hc:    led_seg = 8'hc6;
    4'hd:    led_seg = 8'ha1;
    4'he:    led_seg = 8'h86;
    4'hf:    led_seg = 8'h8e;
    default: led_seg = 8'hc0;
endcase
end

endmodule

hellok

工程师

2012-11-28 23:48:51 打赏

8楼

//*********************************************************
//文件名称： key.v
//说明：      手把手教你学习FPGA—按键篇实验一按键控制LED亮灭
//           按KEY1，数码管在0-9变化
//版本号：    V0.0 2012.11.26
//*********************************************************

module key(sys_clk, rst_n, key, led_seg, led_bit);

input sys_clk, rst_n;
input [7:0] key;
output [7:0] led_seg;
output [7:0] led_bit;

//reg [7:0] led;
reg [3:0] count10;
reg [7:0] led_seg;
wire [7:0] led_bit;
wire key_scan;
reg key_samp;
reg key_samp_r;

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_samp <= 1'b1;
else
      key_samp <= key[0];
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_samp_r <= 1'b1;
else
      key_samp_r <= key_samp;
end

assign key_scan = key_samp_r & (~key_samp);

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      count10 <= 4'd0;//led <= 8'b1111_1111;
else if (key_scan)
      begin
    count10 <= count10 + 1;//led <= ~led;
    if (count10 == 4'd9)
        count10 <= 4'd0;
    end
// else
//      led <= led;
end

always @ (count10)
begin
    case(count10)
   4'd0 : led_seg = 8'hc0;
    4'd1 : led_seg = 8'hf9;
    4'd2 : led_seg = 8'ha4;
    4'd3 : led_seg = 8'hb0;
    4'd4 : led_seg = 8'h99;
    4'd5 : led_seg = 8'h92;
    4'd6 : led_seg = 8'h82;
    4'd7 : led_seg = 8'hf8;
    4'd8 : led_seg = 8'h80;
    4'd9 : led_seg = 8'h90;
    default: led_seg = 8'h86;
endcase
end

assign led_bit = 8'b1111_1110;

endmodule

//*********************************************************
//文件名称： key.v
//说明：      手把手教你学习FPGA—按键篇实验二按键消抖控制LED亮灭
//           按KEY1，数码管在0-9变化
//版本号：    V0.0 2012.11.28
//*********************************************************
module key(sys_clk, rst_n, key, led_seg, led_bit);

input sys_clk, rst_n;
input [7:0] key;
//output [7:0] led;
output [7:0] led_seg;
output [7:0] led_bit;

//reg [7:0] led;
reg [19:0] delay_cnt;
wire key_scan;
wire key_low;
reg key_samp;
reg key_samp_r;
reg key_rst;
reg key_rst_r;
reg [3:0] count10;
reg [7:0] led_seg;

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_samp <= 1'b1;
else
      key_samp <= key[0];
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_samp_r <= 1'b1;
else
      key_samp_r <= key_samp;
end

assign key_scan = key_samp_r & (~key_samp);

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= 20'h0;
else if (key_scan)
      delay_cnt <= 20'h0;
else
      delay_cnt <= delay_cnt + 1'b1;
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_rst <= 1'b1;
else if (delay_cnt == 20'hfffff)
      key_rst <= key[0];
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_rst_r <= 1'b1;
else
      key_rst_r <= key_rst;
end

assign key_low = key_rst_r & (~key_rst);

/*always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      led <= 8'b1111_1111;
else if (key_low)
      led <= ~led;
else
      led <= led;
end*/

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      count10 <= 4'd0;
else if (key_low)
      begin
    count10 <= count10 + 1;
    if (count10 == 4'd9)
        count10 <= 4'd0;
    end
end

assign led_bit = 8'b1111_1110;

endmodule

hellok

工程师

2012-11-29 22:27:08 打赏

9楼

//*********************************************************
//文件名称： buzz.v
//说明：      手把手教你学习FPGA—蜂鸣器篇实验一蜂鸣器发出救护车鸣笛声
//           蜂鸣器发出报警声
//版本号：    V0.0 2012.11.29
//*********************************************************

module buzz(sys_clk, rst_n, beep);

input sys_clk, rst_n;
output beep;

reg beep;
reg [23:0] div_cnt;
reg [14:0] delay_cnt;
wire [14:0] delay_end;

parameter clk_divider0 = 113635;
parameter clk_divider1 = 56817;
assign delay_end = div_cnt[23] ? clk_divider0 : clk_divider1;

always @ (posedge sys_clk or negedge rst_n)   //一种音调时长
begin
    if (!rst_n)
      div_cnt <= 24'd0;
else
      div_cnt <= div_cnt + 1'b1;
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= delay_end;
else if (delay_cnt == 15'd0)
      begin
    beep <= ~beep;
    delay_cnt <= delay_end;
    end
else
      delay_cnt <= delay_cnt - 1'b1;
end

endmodule
//*********************************************************
//文件名称： music.v
//说明：      手把手教你学习FPGA—蜂鸣器篇实验二硬件电子琴
//           自动播放梁祝
//版本号：    V0.0 2012.11.29
//*********************************************************

module music(sys_clk, beep);

input sys_clk;
output beep;

reg beep_r;
reg [7:0] state;
reg [15:0] count, count_end;
reg [23:0] count1;

parameter   L_3 = 16'd75850,
            L_5 = 16'd63776,
            L_6 = 16'd56818,
   L_7 = 16'd50618,
   M_1 = 16'd47774,
   M_2 = 16'd42568,
   M_3 = 16'd37919,
   M_5 = 16'd31888,
   M_6 = 16'd28409,
   H_1 = 16'd23912;
parameter TIME = 12000000;

assign beep = beep_r;

always@(posedge sys_clk)
begin
count <= count + 1'b1;
if(count == count_end)
begin
count <= 16'h0;
beep_r <= !beep_r;
end
end

always @ (posedge sys_clk)
begin
if(count1 < TIME)
  count1 = count1 + 1'b1;
else
begin
  count1 = 24'd0;
  if(state == 8'd66)
   state = 8'd0;
  else
   state = state + 1'b1;
  case(state)
   8'd0,8'd1,8'd2,8'd3:     count_end = L_3;
   8'd4,8'd5,8'd6:                     count_end = L_5;
   8'd7:                       count_end = L_6;
   8'd8,8'd9,8'd10:            count_end = M_1;
   8'd11:         count_end = M_2;
   8'd12:               count_end = L_6;
   8'd13:               count_end = M_1;
   8'd14,8'd15:                   count_end = L_5;
   8'd16:               count_end = M_1;
   8'd17,8'd18:       count_end = L_5;
   8'd19,8'd20,8'd21:              count_end = M_5;
   8'd22:                           count_end = H_1;
   8'd23:                        count_end = M_6;
   8'd24:                  count_end = M_5;
   8'd25:               count_end = M_3;
   8'd26:                        count_end = M_5;
   8'd27,8'd28,8'd29,8'd30,8'd31,
   8'd32,8'd33,8'd34,8'd35,8'd36,8'd37:count_end = M_2;
   8'd38:               count_end = M_3;
   8'd39,8'd40:      count_end = L_7;
   8'd41,8'd42:                count_end = L_6;
   8'd43,8'd44,8'd45:      count_end = L_5;
   8'd46:               count_end = L_6;
   8'd47,8'd48:               count_end = M_1;
   8'd49,8'd50:                count_end = M_2;
   8'd51,8'd52:       count_end = L_3;
   8'd53,8'd54,8'd55:            count_end = M_1;
   8'd56,8'd57:          count_end = L_5;
   8'd58:               count_end = M_1;
   8'd59,8'd60,8'd61,8'd62,8'd63,
   8'd64,8'd65,8'd66:               count_end = L_5;
  endcase
end
end

endmodule

/*module music (sys_clk, rst_n, key, beep);

input sys_clk ,rst_n;
input [7:0] key;
output beep;

reg beep;
reg [15:0] delay_cnt;
reg [15:0] delay_end;

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= 16'd0;
else if ((delay_cnt == delay_end) & (!(delay_end == 16'hffff)))
      begin
    delay_cnt <= 16'd0;
    beep <= ~beep;
    end
else
      delay_cnt <= delay_cnt + 1'b1;
end

always @ (key)
begin
    case (key)
      8'b1111_1110 : delay_end = 16'd47774;
    8'b1111_1101 : delay_end = 16'd42568;
    8'b1111_1011 : delay_end = 16'd37919;
    8'b1111_0111 : delay_end = 16'd35791;
    8'b1110_1111 : delay_end = 16'd31888;
    8'b1101_1111 : delay_end = 16'd28409;
    8'b1011_1111 : delay_end = 16'd25309;
    8'b0111_1110 : delay_end = 16'd23912;
    8'b0111_1101 : delay_end = 16'd21282;
    8'b0111_1011 : delay_end = 16'd18961;
    8'b0111_0111 : delay_end = 16'd17897;
    8'b0110_1111 : delay_end = 16'd15944;
    8'b0101_1111 : delay_end = 16'd14205;
    8'b0011_1111 : delay_end = 16'd12655;
    default : delay_end = 16'd65535;
endcase
end

endmodule
*/

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打赏帖
分享一种检测按键状态的方法被打赏20分
周末总结一下，STM32C0系列的开发经验被打赏50分
【换取手持数字示波器】MicrochipMPLABHarmony框架下定时器配置被打赏20分
【换取手持数字示波器】MicrochipMPLABHarmony框架下PWM配置被打赏20分
【Cortex-M】Systick Timer使用被打赏10分
分享汽车防盗系统的组成与分类（一）被打赏5分
VOFA+波形显示+JYD-31蓝牙发送和解析不定长数据被打赏10分
【换取手持数字示波器】-STM32F4PWM控制LED灯管亮度被打赏22分
【换取手持数字示波器】STM32F4驱动RPR-0521RS照度、接近一体型传感器被打赏23分
宏定义和const关键字定义被打赏5分

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