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hellok FPGA DIY进程贴

hellok
工程师
2012-10-15 22:21:26     打赏
收到东西有几天了，一直比较忙，没怎么整，今天总算焊完了，下载了测试程序进去，提示下载成功，可居然没跑起来，LED一个也不亮，不知道怎么回事,要再找时间查查

10-20 焊得有些问题，先用着吧。点亮了下LED，拍个照看不到效果，就不上图了，简单的很的LED闪烁没什么看的，在7楼
10-24 太慢了，还是闪灯的，跑马灯+流水灯+闪两次，在8楼，就不上图了
11-26 都一个月没更新了，自己都差多不忘了这事。。。。弄了下数码管的显示。
11-28按键控制数码管显示
11-29蜂鸣器

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关键词： hellok     进程    

51FPGA
高工
2012-10-15 22:50:33     打赏
2楼
是下载我上传的下载程序吗？我晶振焊接的是Y2

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hellok
工程师
2012-10-16 08:32:39     打赏
3楼
是你的程序，也是焊的Y2，后来发现刚下载完后工作正常，断电后再上电就不工作了，再重新下载后又工作。本来以为是复位部分的问题，可检查了没发现有什么不正常。

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HXW718059156
高工
2012-10-16 11:15:21     打赏
4楼
不会芯片烧坏了吧？

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hellok
工程师
2012-10-16 18:08:24     打赏
5楼
有可能，烙铁有问题，加热到一定程度烙铁上就有比较高的电压，居然把自己电了一下。。。。。。不过刚下载完能工作至少说明没彻底烧掉

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halibote523
专家
2012-10-17 23:25:28     打赏
6楼
也有可能是你 代码问题

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hellok
工程师
2012-10-20 13:40:12     打赏
7楼

//*********************************************************
//文件名称：  led.v
//说明：      LED闪烁
//版本号：    V0.0  2012.10.19
//*********************************************************

module led (led,clk_50M,rst_n);
output[10:0] led;
input clk_50M;
input rst_n;
reg[10:0] mled;
reg[23:0] cnt;

always @(posedge clk_50M, negedge rst_n)
begin
    if (!rst_n)
        mled <= 11'b01010101010;
    else
    begin
      cnt <= cnt + 1;
    if (cnt == 23'd2500000)
            mled <= ~mled;
    end
end

assign led = mled;
endmodule


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hellok
工程师
2012-10-24 23:56:21     打赏
8楼

//*********************************************************
//文件名称：  huayang.v
//说明：      手把手教你学习FPGA—LED篇 实验五？
//版本号：    V0.0  2012.10.24
//*********************************************************

module huayang (clk, rst_n, led);
input clk, rst_n;
output [10:0] led;

reg [10:0] mled;
reg [24:0] delay_cnt;
reg [1:0] state;
reg [1:0] shs_cnt;

always @ (posedge clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= 25'd0;
  else
      begin
        if (delay_cnt == 25'd24999999)
        delay_cnt <= 25'd0;
    else
        delay_cnt <= delay_cnt + 1'd1;
    end
end

always @ (posedge clk or negedge rst_n)
begin
    if (!rst_n)
      begin
      mled <= 11'b111_1111_1110;
    state <= 2'd0;
    shs_cnt <= 2'd0;
    end
  else
      begin
    if (delay_cnt == 25'd24999999)
        begin
          case (state)
              2'd0:                             //跑马灯
            begin
            mled <= {mled[9:0], led[10]};
        if ( mled == 11'b011_1111_1111)
            begin
            mled <= 11'b111_1111_1111;
                  state <= 2'd1;
            end
          end
          2'd1:                             //流水灯
            begin
            mled <= mled << 1;
        if (mled == 11'b000_0000_0000)
            begin
                  mled <= 11'b111_1111_1111;
          state <= 2'd2;          
            end
          end
      2'd2:                            //流水灯从右到左
            begin
            mled <= mled >> 1;
        if (mled == 11'b000_0000_0000)
            begin
                  mled <= 11'b111_1111_1111;
          state <= 2'd3;          
            end
          end         
        2'd3:                             //闪烁灯
            begin
            mled <= ~mled;
        shs_cnt <= shs_cnt + 1'd1;
        if (shs_cnt == 2'd3)
            begin
              shs_cnt <= 1'd0;
            mled <= 11'b111_1111_1110;
            state <= 2'd0;
          end
          end
        default:
            mled <= 11'b010_1100_1100;
          endcase
        end
    end
end

assign led = mled;

endmodule


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hellok
工程师
2012-11-26 23:06:30     打赏
9楼

//*********************************************************
//文件名称：  seg_sta.v
//说明：      手把手教你学习FPGA—数码管篇 实验一 数码管静态显示
//           拨动拨码开关控制数码管显示
//版本号：    V0.0  2012.11.20
//*********************************************************

module seg_sta (sys_clk, rst_n, led_seg, led_bit, sw_dip);

input sys_clk, rst_n;
input [7:0] sw_dip;
output [7:0] led_seg;
output [7:0] led_bit;

reg [7:0] sw_buf;
reg [7:0] led_seg;
wire [7:0] led_bit;
//reg [3:0] disp_dat; //显示数据寄存器;
reg [25:0] delay_cnt;

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= 26'd0;
  else
      begin
    if (delay_cnt == 26'd49999999)
        delay_cnt <= 26'd0;
    else
        delay_cnt <= delay_cnt + 1'b1;
      end
end

/*always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      disp_dat <= 4'd0;
  else
      begin
    if (delay_cnt == 26'd49999999)
        disp_dat <= disp_dat + 1'b1;
    else
        disp_dat <= disp_dat;
    end
end*/

always @ (sw_dip)
begin
    sw_buf = sw_dip;
    case (sw_buf)
      8'b11111110: led_seg = 8'hf9;
        8'b11111101: led_seg = 8'ha4;
        8'b11111011: led_seg = 8'hb0;
        8'b11110111: led_seg = 8'h99;
        8'b11101111: led_seg = 8'h92;
        8'b11011111: led_seg = 8'h82;
        8'b10111111: led_seg = 8'hf8;
        8'b01111111: led_seg = 8'h80;
        default:     led_seg = 8'h86;
  endcase
end

/*always @ (disp_dat)
begin
    case (disp_dat)
      4'h0 : led_seg = 8'hc0;
    4'h1 : led_seg = 8'hf9;
    4'h2 : led_seg = 8'ha4;
    4'h3 : led_seg = 8'hb0;
    4'h4 : led_seg = 8'h99;
    4'h5 : led_seg = 8'h92;
    4'h6 : led_seg = 8'h82;
    4'h7 : led_seg = 8'hf8;
    4'h8 : led_seg = 8'h80;
    4'h9 : led_seg = 8'h90;
    4'ha : led_seg = 8'h88;
    4'hb : led_seg = 8'h83;
    4'hc : led_seg = 8'hc6;
    4'hd : led_seg = 8'ha1;
    4'he : led_seg = 8'h86;
    4'hf : led_seg = 8'h8e;
  endcase
end*/

assign led_bit = 8'b00000000;

endmodule


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hellok
工程师
2012-11-26 23:07:26     打赏
10楼

//*********************************************************
//文件名称：  shansh.v
//说明：      手把手教你学习FPGA—数码管篇 实验二 数码管动态显示
//           数码管动态显示0-7例程，直接在上面更改增加模60计数功能
//版本号：    V0.0  2012.11.26
//*********************************************************

module seg_dyn (sys_clk, rst_n, led_seg, led_bit);

input sys_clk;
input rst_n;
output [7:0] led_seg;
output [7:0] led_bit;

reg [7:0] led_seg;
reg [7:0] led_bit;
reg [4:0] dataout_buf;
reg [2:0] disp_dat;
reg [15:0] delay_cnt;
reg [25:0] delay_1s;
reg [5:0] count60;
reg [3:0] count60_ge, count60_shi;

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= 16'd0;
  else
      begin
    if (delay_cnt == 16'd49999)
        delay_cnt <= 16'd0;
    else
        delay_cnt <= delay_cnt + 1'b1;
    end
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      disp_dat <= 4'd0;
  else
      begin
    if (delay_cnt == 16'd49999)
        disp_dat <= disp_dat + 1'b1;
    else
        disp_dat <= disp_dat;
    end
end

always @ (posedge sys_clk or negedge rst_n)   //1秒计数
begin
    if (!rst_n)
      delay_1s <= 26'd0;
  else
      begin
    if (delay_1s == 26'd49999999)
        delay_1s <= 26'd0;
    else
        delay_1s <= delay_1s + 1'b1;
    end
end

always @ (posedge sys_clk or negedge rst_n)   //模60计数；
begin
    if (!rst_n)
      count60 <= 6'd0;
  else
      begin
    if (count60 == 6'd60)
        count60 <= 0;
    else
        begin
    if (delay_1s == 26'd49999999)
        count60 <= count60 + 1'b1;
    else
        count60 <= count60;
    end
    end
end

always @ (disp_dat)
begin
    case (disp_dat)
      3'b000:    led_bit = 8'b1111_1110;
    3'b001:    led_bit = 8'b1111_1101;
    3'b010:    led_bit = 8'b1111_1011;
    3'b011:    led_bit = 8'b1111_0111;
    3'b100:    led_bit = 8'b1110_1111;
    3'b101:    led_bit = 8'b1101_1111;
    3'b110:    led_bit = 8'b1011_1111;
    3'b111:    led_bit = 8'b0111_1111;
    default:   led_bit = 8'b1111_1110;
  endcase
end

always @ (led_bit)
begin
    count60_ge <= count60 % 10;
  count60_shi <= count60 / 10;
    case (led_bit)
      8'b1111_1110:    dataout_buf = count60_ge;//0;    //模60计数的个位；
    8'b1111_1101:    dataout_buf = count60_shi;//1;
    8'b1111_1011:    dataout_buf = 2;
    8'b1111_0111:    dataout_buf = 3;
    8'b1110_1111:    dataout_buf = 4;
    8'b1101_1111:    dataout_buf = 5;
    8'b1011_1111:    dataout_buf = 6;
    8'b0111_1111:    dataout_buf = 7;
    default:         dataout_buf = 8;
  endcase
end

always @ (dataout_buf)
begin
    case (dataout_buf)
      4'h0:    led_seg = 8'hc0;
    4'h1:    led_seg = 8'hf9;
    4'h2:    led_seg = 8'ha4;
    4'h3:    led_seg = 8'hb0;
    4'h4:    led_seg = 8'h99;
    4'h5:    led_seg = 8'h92;
    4'h6:    led_seg = 8'h82;
    4'h7:    led_seg = 8'hf8;
    4'h8:    led_seg = 8'h80;
    4'h9:    led_seg = 8'h90;
    4'ha:    led_seg = 8'h88;
    4'hb:    led_seg = 8'h83;
    4'hc:    led_seg = 8'hc6;
    4'hd:    led_seg = 8'ha1;
    4'he:    led_seg = 8'h86;
    4'hf:    led_seg = 8'h8e;
    default: led_seg = 8'hc0;
  endcase
end

endmodule


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