由于买了板子后就外出做课题了,也没带板子所以一直到最近才开始做,幸亏延期了,呵呵;经过近2周左右的努力学习,已经做到了12864显示了,从明天起陆续上传视频和源代码;让版主费心了,实在是不好意思。
希望版主针对状态机专门做一个专题教程,那就太好了,呵呵
//程序一
module led1(LED);
output[7:0] LED;
assign LED=8'b10101010;
endmodule
//程序二
module led1(LED);
output[7:0] LED;
reg [7:0] LED;
always
begin
LED=8'b10101010;
endmodule
//程序三 一个always
//该程序为1s中闪烁,晶振为50Mhz,20ns,所以1s=20*(10^-9)*5*10^7;而5*10^7=10 1111 1010 1111 0000 1000 0000b至少需要26位的位宽
module led1(CLK,RESET,LED);
//????????
input CLK;//?????50Mhz
input RESET;//??????????
output [7:0]LED;//LED????
//?????
reg [7:0] LED;//led???
reg [25:0] delay_cnt;//?????
//????
always@(posedge CLK or negedge RESET)
if(!RESET)
begin
delay_cnt<=26'd0;//???25??????0
LED<=8'b11111111;//???25??????0
end
else
begin
if (delay_cnt==26'd49999999)
begin
delay_cnt<=26'd0;
LED=~LED;
end
else
begin
delay_cnt<=delay_cnt+1'b1;
end
end
endmodule
//程序四 两个always
module led1(CLK,RESET,LED);
//????????
input CLK;//?????50Mhz
input RESET;//??????????
output [7:0] LED;//LED????
//?????
reg [7:0] LED;//led???
reg [25:0] delay_cnt;//?????
//????
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt<=26'd0;//???25??????0
else
begin
if (delay_cnt==26'd49999999)
delay_cnt<=26'd0;
else
delay_cnt<=delay_cnt+1'b1;
end
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
LED<=8'b11111111;//???25??????0
else
begin
if (delay_cnt==26'd49999999)
LED=~LED;
else
LED<=LED;
end
end
endmodule
LED 1s闪烁
module led1(CLK,RESET,LED);
//????????
input CLK;//?????50Mhz
input RESET;//??????????
output [7:0] LED;//LED????
//?????
reg [7:0] LED;//led???
reg [25:0] delay_cnt;//?????
//????
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt<=26'd0;//???25??????0
else
begin
if (delay_cnt==26'd49999999)
delay_cnt<=26'd0;
else
delay_cnt<=delay_cnt+1'b1;
end
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
LED<=8'b11111111;//???25??????0
else
begin
if (delay_cnt==26'd49999999)
LED=~LED;
else
LED<=LED;
end
end
endmodule
http://player.youku.com/player.php/sid/XNTI4NzIyNDYw/v.swf
花样流水
module led1(CLK,RESET,LED);
//????????
input CLK;//?????50Mhz
input RESET;//??????????
output [7:0] LED;//LED????
//?????
reg [7:0] LED;//led???
reg [25:0] delay_cnt;//?????
reg [4:0] state;
//????
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt<=26'd0;//???25??????0
else
begin
if (delay_cnt==26'd24999999)
delay_cnt<=26'd0;
else
delay_cnt<=delay_cnt+1'b1;
end
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
LED<=8'b11111111;//???25??????0
else
begin
case(state)
5'b00000: LED=8'b11111111;
5'b00001: LED=8'b00000000;
5'b00010: LED=8'b00000001;
5'b00011: LED=8'b00000011;
5'b00100: LED=8'b00000111;
5'b00101: LED=8'b00001111;
5'b00110: LED=8'b00011111;
5'b00111: LED=8'b00111111;
5'b01001: LED=8'b01111111;
5'b01010: LED=8'b00000000;
5'b01011: LED=8'b11111111;
5'b01100: LED=8'b10000000;
5'b01101: LED=8'b01000000;
5'b01110: LED=8'b00100000;
5'b01111: LED=8'b00010000;
5'b10000: LED=8'b00001000;
5'b10000: LED=8'b00000100;
5'b10001: LED=8'b00000010;
5'b10010: LED=8'b00000001;
5'b10011: LED=8'b00000000;
5'b10100: LED=8'b01111110;
5'b10101: LED=8'b10111101;
5'b10110: LED=8'b11011011;
5'b10111: LED=8'b11100111;
5'b11001: LED=8'b11111111;
5'b11010: LED=8'b11100111;
5'b11011: LED=8'b11011011;
5'b11100: LED=8'b10111101;
5'b11101: LED=8'b01111110;
5'b11110: LED=8'b11111111;
5'b11111: LED=8'b00000000;
endcase
state=state+1;
end
end
endmodule
数码管
2-1 1~f静态显示
module smg(CLK,RESET,SEG,DIG);
//????????
input CLK;//?????50Mhz
input RESET;//??????????
output [7:0] SEG;
output [7:0] DIG;
//?????
reg [7:0] SEG;
wire [7:0] DIG;
reg [3:0] dat;
reg [25:0] delay_cnt;//?????
//????
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt<=26'd0;//???25??????0
else
begin
if (delay_cnt==26'd49999999)
delay_cnt<=26'd0;
else
delay_cnt<=delay_cnt+1'b1;
end
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
dat<=4'd0;
else
begin
if(delay_cnt==26'd49999999)
dat<=dat+1'b1;
else
dat<=dat;
end
end
always@(dat)
begin
case(dat)
4'h0: SEG = 8'hc0;
4'h1: SEG = 8'hf9;
4'h2: SEG = 8'ha4;
4'h3: SEG = 8'hb0;
4'h4: SEG = 8'h99;
4'h5: SEG = 8'h92;
4'h6: SEG = 8'h82;
4'h7: SEG = 8'hf8;
4'h8: SEG = 8'h80;
4'h9: SEG = 8'h90;
4'ha: SEG = 8'h88;
4'hb: SEG = 8'h83;
4'hc: SEG = 8'hc6;
4'hd: SEG = 8'ha1;
4'he: SEG = 8'h86;
4'hf: SEG = 8'h8e;
endcase
end
assign DIG=8'b00000000;
endmodule
2-2拨码数码管
module smg(CLK,RESET,SEG,DIG,SW);
//????????
input CLK;//?????50Mhz
input RESET;//??????????
input [7:0] SW;
output [7:0] SEG;
output [7:0] DIG;
//?????
reg [7:0] SEG;
wire [7:0] DIG;
reg [3:0] dat;
reg [25:0] delay_cnt;//?????
//????
always@(negedge SW or negedge RESET)
begin
case(SW)
8'b11111111:dat=4'h0;
8'b11111110:dat=4'h1;
8'b11111101:dat=4'h2;
8'b11111011:dat=4'h3;
8'b11110111:dat=4'h4;
8'b11101111:dat=4'h5;
8'b11011111:dat=4'h6;
8'b10111111:dat=4'h7;
8'b01111111:dat=4'h8;
default: dat=4'hf;
endcase
end
always@(dat)
begin
case(dat)
4'h0: SEG = 8'hc0;
4'h1: SEG = 8'hf9;
4'h2: SEG = 8'ha4;
4'h3: SEG = 8'hb0;
4'h4: SEG = 8'h99;
4'h5: SEG = 8'h92;
4'h6: SEG = 8'h82;
4'h7: SEG = 8'hf8;
4'h8: SEG = 8'h80;
4'h9: SEG = 8'h90;
4'ha: SEG = 8'h88;
4'hb: SEG = 8'h83;
4'hc: SEG = 8'hc6;
4'hd: SEG = 8'ha1;
4'he: SEG = 8'h86;
4'hf: SEG = 8'h8e;
endcase
end
assign DIG=8'b00000000;
endmodule
2-3 60s计时
module smg(CLK,RESET,SEG,DIG);
//????????
input CLK;//?????50Mhz
input RESET;//??????????
output [7:0] SEG;
output [7:0] DIG;
//?????
reg [7:0] SEG;
reg [7:0] DIG;
reg [4:0] dbuf;
reg dat;
reg [25:0] delay_cnt;//?????
reg [25:0] delay_cnt1;
reg [3:0] cntl;
reg [2:0] cnth;
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt<=26'd0;//???25??????0
else
begin
if (delay_cnt==26'd49999999)
delay_cnt<=26'd0;
else
delay_cnt<=delay_cnt+1'b1;
end
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
cntl<=4'd0;
else if(delay_cnt==26'd49999999)
if(cntl==4'd9) cntl<=4'd0;
else cntl<=cntl+4'd1;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
cnth<=3'd0;
else if(cntl==4'd9 && delay_cnt==26'd49999999)
if(cnth==3'd5) cnth<=3'd0;
else cnth<=cnth+3'd1;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt1<=26'd0;//???25??????0
else
begin
if (delay_cnt1==26'd499999)
delay_cnt1<=26'd0;
else
delay_cnt1<=delay_cnt1+1'b1;
end
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
dat<=1'b0;
else if(delay_cnt1==26'd499999)
dat<=~dat;
end
always@(dat)
begin
case(dat)
2'b00:DIG=8'b11111110;
2'b01:DIG=8'b11111101;
default:DIG=8'b11111111;
endcase
end
always@(DIG or cntl or cnth)
begin
case(DIG)
8'b11111110:dbuf<=cntl;
8'b11111101:dbuf<=cnth;
default:dbuf<=5'd0;
endcase
end
always@(dbuf)
begin
case(dbuf)
4'h0: SEG = 8'hc0;
4'h1: SEG = 8'hf9;
4'h2: SEG = 8'ha4;
4'h3: SEG = 8'hb0;
4'h4: SEG = 8'h99;
4'h5: SEG = 8'h92;
4'h6: SEG = 8'h82;
4'h7: SEG = 8'hf8;
4'h8: SEG = 8'h80;
4'h9: SEG = 8'h90;
4'ha: SEG = 8'h88;
4'hb: SEG = 8'h83;
4'hc: SEG = 8'hc6;
4'hd: SEG = 8'ha1;
4'he: SEG = 8'h86;
4'hf: SEG = 8'h8e;
default:SEG=8'hc0;
endcase
end
endmodule
http://v.youku.com/v_show/id_XNTI4MjcwODY0.html
3.按键
3-1按键未除抖module key(CLK,RESET,LED,KEY);
input CLK;
input RESET;
input KEY;
output LED;
reg LED;
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
LED<=1'b1;
else if(!KEY)
LED<=~LED;
else
LED<=LED;
end
endmodule http://player.youku.com/player.php/sid/XNTI4MjY0NDA0/v.swf
3-2按键未除抖数码管
module key(CLK,RESET,KEY,SEG,DIG);
input CLK;
input RESET;
input KEY;
output [7:0] SEG;
output [7:0] DIG;
reg [7:0] SEG;
wire [7:0] DIG;
reg [3:0] dat;
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
dat<=1'b1;
else if(!KEY)
dat<=dat+1'b1;
else
dat<=dat;
end
always@(dat)
begin
case(dat)
4'h0: SEG = 8'hc0;
4'h1: SEG = 8'hf9;
4'h2: SEG = 8'ha4;
4'h3: SEG = 8'hb0;
4'h4: SEG = 8'h99;
4'h5: SEG = 8'h92;
4'h6: SEG = 8'h82;
4'h7: SEG = 8'hf8;
4'h8: SEG = 8'h80;
4'h9: SEG = 8'h90;
4'ha: SEG = 8'h88;
4'hb: SEG = 8'h83;
4'hc: SEG = 8'hc6;
4'hd: SEG = 8'ha1;
4'he: SEG = 8'h86;
4'hf: SEG = 8'h8e;
endcase
end
assign DIG=8'b11111110;
endmodule
3-3按键除抖
module key(CLK,RESET,KEY,LED);
input CLK;
input RESET;
input KEY;
output LED;
reg LED;
reg [19:0] delay_cnt;
wire kscan;
wire klow;
reg ksamp;
reg ksampr;
reg krst;
reg krstr;
//edge detect
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
ksamp<=1'b1;
else
ksamp<=KEY;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
ksampr<=1'b1;
else
ksampr<=ksamp;
end
assign kscan=ksampr&(~ksamp);
//delay 20ms
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt<=20'h0;
else if(kscan)
delay_cnt<=20'h0;
else
delay_cnt<=delay_cnt+1'b1;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
krst<=1'b1;
else if(delay_cnt==20'hfffff)
krst<=KEY;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
krstr<=1'b1;
else
krstr<=krst;
end
assign klow=krstr&(~krst);
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
LED<=1'b1;
else if(klow)
LED<=~LED;
else
LED<=LED;
end
endmodule
http://player.youku.com/player.php/sid/XNTI4MjYwNzAw/v.swf
3-4 按键除抖+数码管
module key(CLK,RESET,KEY,SEG,DIG);
input CLK;
input RESET;
input KEY;
output [7:0] SEG;
output [7:0] DIG;
reg LED;
reg [19:0] delay_cnt;
wire kscan;
wire klow;
reg ksamp;
reg ksampr;
reg krst;
reg krstr;
reg [7:0] SEG;
wire [7:0] DIG;
reg [3:0] dat;
//edge detect
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
ksamp<=1'b1;
else
ksamp<=KEY;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
ksampr<=1'b1;
else
ksampr<=ksamp;
end
assign kscan=ksampr&(~ksamp);
//delay 20ms
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
delay_cnt<=20'h0;
else if(kscan)
delay_cnt<=20'h0;
else
delay_cnt<=delay_cnt+1'b1;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
krst<=1'b1;
else if(delay_cnt==20'hfffff)
krst<=KEY;
end
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
krstr<=1'b1;
else
krstr<=krst;
end
assign klow=krstr&(~krst);
always@(posedge CLK or negedge RESET)
begin
if(!RESET)
dat<=1'b1;
else if(klow)
dat<=dat+1'b1;
else
dat<=dat;
end
always@(dat)
begin
case(dat)
4'h0: SEG = 8'hc0;
4'h1: SEG = 8'hf9;
4'h2: SEG = 8'ha4;
4'h3: SEG = 8'hb0;
4'h4: SEG = 8'h99;
4'h5: SEG = 8'h92;
4'h6: SEG = 8'h82;
4'h7: SEG = 8'hf8;
4'h8: SEG = 8'h80;
4'h9: SEG = 8'h90;
4'ha: SEG = 8'h88;
4'hb: SEG = 8'h83;
4'hc: SEG = 8'hc6;
4'hd: SEG = 8'ha1;
4'he: SEG = 8'h86;
4'hf: SEG = 8'h8e;
endcase
end
assign DIG=8'b11111110;
endmodule
http://player.youku.com/player.php/sid/XNTI4MjY1NDY0/v.swf
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