ModusToolbox中提供BSP Assistant工具用于管理开发板的硬件驱动,集成Device Configurator、QSPI Configrator、驱动库管理以及应用设置等功能,用于配置硬件相关的驱动和工程设置。BSP Assistant的使用可以查看官方的手册。

在ModusToolbox Eclipse IDE中,通过工程的快速访问菜单启动BSP Assistant配置工具,或者通过BSP Configurators访问单独的配置工具。

PSOC Edge E84 AI Kit属于官方的开发板,官方为硬件适配相应的BSP,通过查看开发板相应的BSP设置熟悉BSP Assistant的设置。开发板板载PSE846GPS2DBZC4主控和LBEE5HY2FY(CYW55513)Wifi蓝牙双模协处理器。BSP Assistant中的Devices菜单中设置有芯片的型号。

Defines菜单中添加的额外的宏定义

Components菜单设置与无线协处理相关的组件配置

Libraries菜单显示添加的驱动库,右侧的删除图标能移除相应的库,Add Library按钮添加驱动库。

Device Configurator菜单,通过启动Device Configurator配置MCU的外设。

Device Configurator中配置MCU外设、引脚、时钟、内存、DMA等不同部分的参数

QSPI Configurator菜单,通过启动QSPI Configurator配置外部存储的配置。

QSPI Configurator中配置外部存储器件的通讯协议以及存储容量。

从QSPI Configurator中可以看出外部的HyperRAM器件没有配置,以添加HyperRAM器件的配置说明BSP Assistant中HyperRAM相关的设置过程。
2、Device Configurator和QSPI Configurator配置HyperRAM硬件原理图中显示外挂有Octal SPI HyperRAM,芯片型号为S70KS1283GABHI020。


Device Configurator的Peripherals界面中显示QSPI1外接HyperRAM,HyperRAM的片选引脚使用SPI Slave Select2。

Clocks选项卡中显示QSPI1时钟的配置信息

Memeory界面显示开发板内存空间的分配情况,显示HyperRAM的地址空间没有添加到配置中,需要在QSPI Configurator中配置HyperRAM存储器件的信息。

打开QSPI Configurator,添加HyperRAM配置,芯片型号为S70KS1283GABHI020,通讯协议为Octal SPI,QSPI1的片选信号使用SPI Slave Select2。查看PSOC Edge E84的架构手册,其中显示SMIF1管理地址空间在Non-Secure模式下的访问地址为0x64000000起始。

根据以上信息,QSPI Configurator中,添加HyperRAM的配置如下

重新加载Device Configurator,其中出现待分配的HyperRAM地址空间

在SMIF1对应的存储区域中添加分区

添加的分区,将HyperRAM的16MB空间分配给M55内核使用

CM55内核访问HyperRAM的地址空间时,需要添加CM55访问HyperRAM的MPU设置。

保存并生成代码。
选中工程启动Library Manager,在proj_cm55中添加retarget-io和serial memory驱动库。


proj_cm55工程中添加retarget_io_init.c/h初始化串口信息打印组件,用于CM55控制串口输出信息。
retarget_io_init.h
#ifndef _RETARGET_IO_INIT_H_
#define _RETARGET_IO_INIT_H_
/*******************************************************************************
* Header Files
*******************************************************************************/
#include "cybsp.h"
#include "mtb_hal.h"
#include "cy_retarget_io.h"
#include "mtb_syspm_callbacks.h"
/*******************************************************************************
* Macros
*******************************************************************************/
/* retarget-io deepsleep callback macros */
#define DEBUG_UART_RTS_PORT (NULL)
#define DEBUG_UART_RTS_PIN (0U)
/* Default syspm callback configuration elements */
#define SYSPM_SKIP_MODE (0U)
#define SYSPM_CALLBACK_ORDER (1U)
/*******************************************************************************
* Function prototypes
*******************************************************************************/
void init_retarget_io(void);
/*******************************************************************************
* Function Name: handle_app_error
********************************************************************************
* Summary:
* User defined error handling function
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
__STATIC_INLINE void handle_app_error(void)
{
/* Disable all interrupts. */
__disable_irq();
CY_ASSERT(0);
/* Infinite loop */
while(true);
}
#endif /* _RETARGET_IO_INIT_H_ */retarget_io_init.c
/*******************************************************************************
* Header Files
*******************************************************************************/
#include "retarget_io_init.h"
/*******************************************************************************
* Global Variables
*******************************************************************************/
/* For the RetargetIO (Debug UART) usage. */
static cy_stc_scb_uart_context_t DEBUG_UART_context;
static mtb_hal_uart_t DEBUG_UART_hal_obj;
/* Retarget-io deepsleep callback parameters */
#if (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP)
/* Context reference structure for Debug UART */
static mtb_syspm_uart_deepsleep_context_t retarget_io_syspm_ds_context =
{
.uart_context = &DEBUG_UART_context,
.async_context = NULL,
.tx_pin =
{
.port = CYBSP_DEBUG_UART_TX_PORT,
.pinNum = CYBSP_DEBUG_UART_TX_PIN,
.hsiom = CYBSP_DEBUG_UART_TX_HSIOM
},
.rts_pin =
{
.port = DEBUG_UART_RTS_PORT,
.pinNum = DEBUG_UART_RTS_PIN,
.hsiom = HSIOM_SEL_GPIO
}
};
/* SysPm callback parameter structure for Debug UART */
static cy_stc_syspm_callback_params_t retarget_io_syspm_cb_params =
{
.context = &retarget_io_syspm_ds_context,
.base = CYBSP_DEBUG_UART_HW
};
/* SysPm callback structure for Debug UART */
static cy_stc_syspm_callback_t retarget_io_syspm_cb =
{
.callback = &mtb_syspm_scb_uart_deepsleep_callback,
.skipMode = SYSPM_SKIP_MODE,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &retarget_io_syspm_cb_params,
.prevItm = NULL,
.nextItm = NULL,
.order = SYSPM_CALLBACK_ORDER
};
#endif /* (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP) */
/*******************************************************************************
* Function Name: init_retarget_io
********************************************************************************
* Summary:
* User defined function to initialize the debug UART.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void init_retarget_io(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
/* Initialize the SCB UART */
result = (cy_rslt_t)Cy_SCB_UART_Init(CYBSP_DEBUG_UART_HW,
&CYBSP_DEBUG_UART_config,
&DEBUG_UART_context);
/* UART initialization failed. Stop program execution. */
if (CY_RSLT_SUCCESS != result)
{
handle_app_error();
}
/* Enable the SCB UART */
Cy_SCB_UART_Enable(CYBSP_DEBUG_UART_HW);
result = mtb_hal_uart_setup(&DEBUG_UART_hal_obj,
&CYBSP_DEBUG_UART_hal_config,
&DEBUG_UART_context, NULL);
/* UART setup failed. Stop program execution. */
if (CY_RSLT_SUCCESS != result)
{
handle_app_error();
}
/* Initialize retarget-io to use the debug UART port. */
result = cy_retarget_io_init(&DEBUG_UART_hal_obj);
/* retarget-io initialization failed. Stop program execution. */
if (CY_RSLT_SUCCESS != result)
{
handle_app_error();
}
#if (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP)
/* UART SysPm callback registration for retarget-io */
Cy_SysPm_RegisterCallback(&retarget_io_syspm_cb);
#endif /* (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP) */
}main.c中添加串口数据打印和QSPI HyperRAM驱动相关的头文件、宏定义和变量
/******************************************************************************* * Header File *******************************************************************************/ #include "cybsp.h" #include "retarget_io_init.h" #include "cycfg_qspi_memslot.h" #include "mtb_serial_memory.h" /******************************************************************************* * Macros *******************************************************************************/ /* The timeout value in microsecond used to wait for core to be booted */ #define CM55_BOOT_WAIT_TIME_USEC (10U) #define SMIF_INIT_TIMEOUT_USEC (1000u) /* 1ms SMIF init timeout */ #define EXT_HYPERRAM_ADDR ((uint32_t)0x64400000) #define TEST_ADDRESS 0 // start from zero address #define TEST_BUF_SIZE 256 /******************************************************************************* * Global Variables *******************************************************************************/ static mtb_serial_memory_t serial_memory_obj; static cy_stc_smif_mem_context_t smif_mem_context; static cy_stc_smif_mem_info_t smif_mem_info;
QSPI1 HyperRAM的初始化函数以及读写测试函数定义如下
/******************************************************************************
* Function Name: check_status
*******************************************************************************
* Summary:
*
* Prints the message, indicates the non-zero status by turning the LED on, and
* asserts the non-zero status.
*
* Parameters:
*
* message: Message to print if status is non-zero.
* status: Status for evaluation.
*
* Return:
* void
*
******************************************************************************/
static void check_status(char *message, uint32_t status)
{
if (status)
{
printf("\n\r====================================================\n\r");
printf("\n\rFAIL: %s\n\r", message);
printf("Error Code: 0x%x\n\r", (int) status);
printf("\n\r====================================================\n\r");
}
}
/*******************************************************************************
* Function Name: smif_ospi_psram_init
********************************************************************************
* Summary:
* Initialize SMIF for PSRAM (QSPI Core 1) and set-up serial memory interfeace
*
* Parameters:
* none
*
* Return:
* void
*
*******************************************************************************/
static void smif_ospi_psram_init(void)
{
cy_rslt_t result;
/* Disable SMIF Block for reconfiguration. */
Cy_SMIF_Disable(CYBSP_SMIF_CORE_1_PSRAM_HW);
/* Initialize SMIF-1 Peripheral. */
result = Cy_SMIF_Init((CYBSP_SMIF_CORE_1_PSRAM_hal_config.base),
(CYBSP_SMIF_CORE_1_PSRAM_hal_config.config),
SMIF_INIT_TIMEOUT_USEC, &smif_mem_context.smif_context);
check_status("Cy_SMIF_Init failed", result);
/* Configure Data Select Option for SMIF-1 */
Cy_SMIF_SetDataSelect(CYBSP_SMIF_CORE_1_PSRAM_hal_config.base,
smif1BlockConfig.memConfig[0]->slaveSelect,
smif1BlockConfig.memConfig[0]->dataSelect);
/* Enable the SMIF_CORE_1 block. */
Cy_SMIF_Enable(CYBSP_SMIF_CORE_1_PSRAM_hal_config.base, &smif_mem_context.smif_context);
/* Set-up serial memory. */
result = mtb_serial_memory_setup(&serial_memory_obj,
MTB_SERIAL_MEMORY_CHIP_SELECT_2,
CYBSP_SMIF_CORE_1_PSRAM_hal_config.base,
CYBSP_SMIF_CORE_1_PSRAM_hal_config.clock,
&smif_mem_context,
&smif_mem_info,
&smif1BlockConfig);
check_status("serial memory setup failed", result);
}
static void ReadWriteTest(void)
{
uint32_t i;
volatile uint32_t *pBuf;
/* payload data 0xAAAA5555 */
pBuf = (volatile uint32_t *)EXT_HYPERRAM_ADDR;
for (i = 0; i < TEST_BUF_SIZE; i++)
{
pBuf[i] = 0xAAAA5555;
}
//SCB_CleanInvalidateDCache();
printf("physical address: %08X, size: %dbyte, display: %d details: \r\n", EXT_HYPERRAM_ADDR + TEST_ADDRESS, TEST_BUF_SIZE * 4, TEST_BUF_SIZE * 4);
/* print data */
pBuf = (uint32_t *) (EXT_HYPERRAM_ADDR + TEST_ADDRESS);
for (i = 0; i < TEST_BUF_SIZE; i++)
{
printf(" %04X", pBuf[i]);
if ((i & 7) == 7)
{
printf("\r\n"); /* 32byte display per line */
}
else if ((i & 7) == 3)
{
printf(" - ");
}
}
}main.c中调用初始化串口重定向模块、HyperRAM初始化函数,并调用HyperRAM的数据读写函数。
int main(void)
{
cy_rslt_t result;
/* Initialize the device and board peripherals. */
result = cybsp_init();
/* Board init failed. Stop program execution. */
if (CY_RSLT_SUCCESS != result)
{
/* Disable all interrupts. */
__disable_irq();
CY_ASSERT(0);
/* Infinite loop */
while(true);
}
/* Initialize retarget-io middleware */
init_retarget_io();
/* Enable global interrupts. */
__enable_irq();
/* Initialize PSRAM and set-up serial memory */
smif_ospi_psram_init();
check_status("smif_ospi_psram_init error", (uint32_t)result);
/* Enable XIP mode for the SMIF memory slot associated with the PSRAM. */
result = mtb_serial_memory_enable_xip(&serial_memory_obj, true);
check_status("mtb_serial_memory_enable_xip: failed", result);
/* Enable write for the SMIF memory slot associated with the PSRAM. */
result = mtb_serial_memory_set_write_enable(&serial_memory_obj, true);
check_status("mtb_serial_memory_set_write_enable: failed", result);
printf("****************** "
"PSOC Edge MCU M55: HyperRAM Test "
"****************** \r\n\n");
ReadWriteTest();
/* Put the CPU to Deep Sleep. */
for (;;)
{
Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);
}
}烧录程序到开发板,串口输出的信息如下,HyperRAM的读写测试成功。

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