EEPW论坛

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TEST is
port(
CLK:in STD_LOGIC;
DataBus: inout STD_LOGIC_VECTOR(7 downto 0);
WR: in STD_LOGIC;
RD: in STD_LOGIC
);
end TEST;
architecture TEST_arch of TEST is
signal BUS_S:STD_LOGIC_VECTOR(7 downto 0);
signal BUSOE:STD_LOGIC;
begin
process (CLK)
BEGIN
IF BUSOE = '1' THEN
DataBus <= "ZZZZZZZZ";
ELSE
DataBus <= BUS_S;
END IF;
END PROCESS;
process (CLK)
variable State:integer range 3 downto 0;
variable Data:STD_LOGIC_VECTOR(7 downto 0);
begin
IF CLK'EVENT AND CLK ='1' THEN
case State is
when 0 =>
BUSOE <= '1';
if WR = '0' AND RD = '1' then --WRITE
Data := DataBus ;
State := 1;
elsif WR = '1' AND RD = '0' then --READ
BUS_S <= Data;
BUSOE <= '0';
State := 2;
end if;
when 1 =>
if WR = '1' AND RD = '1' then
State := 0;
end if;
when 2 =>
if WR = '1' AND RD = '1' then
BUSOE <= '1';
State := 0;
end if;
when 3 => --idle state
State := 0;
end case;
END IF;
end process;
end TEST_arch;