EEPW论坛

library ieee; use ieee.std_logic_1164.all; ENTITY CNT IS PORT ( clk_38m88: in std_logic; reset: in std_logic; clk_8k_out: out std_logic; clk_19m44_out: out std_logic ); END CNT; ARCHITECTURE to_19m44 OF CNT IS SIGNAL clk_19m44_buf : STD_LOGIC; BEGIN PROCESS (clk_38m88, reset) BEGIN IF (reset = '0') THEN clk_19m44_buf <= '0'; ELSIF (clk_38m88'event and clk_38m88 = '1') THEN clk_19m44_buf <= not clk_19m44_buf; END IF; END PROCESS; clk_19m44_out <= clk_19m44_buf; END to_19m44; ARCHITECTURE to_8k OF CNT IS SIGNAL clk_8k_buf : STD_LOGIC; BEGIN PROCESS (clk_38m88, reset) VARIABLE div_cnt : integer range 0 to 2488; BEGIN IF (reset = '0') THEN clk_8k_buf <= '1'; div_cnt := 0; ELSIF (clk_38m88'event and clk_38m88 = '1') THEN IF (div_cnt = 2488) THEN div_cnt := 0; clk_8k_buf <= not clk_8k_buf; ELSE div_cnt := div_cnt + 1; clk_8k_buf <= clk_8k_buf; END IF; END IF; END PROCESS; clk_8k_out <= clk_8k_buf; END to_8k; 这段代码为啥编译时说clk_19m44_out没有驱动呢。 如果把8k这个放前面编译时就会提示clk_8k_out没有驱动。 这是为啥呀，不明白呀。