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// Latch Inference
// download from: http://www.fpga.com.cn 

module latchinf(enable, data, q);

    input enable, data;
    output q;
    reg q;

    always @(enable or data)
	if (enable)
		q <= data;

endmodule
12位寄存器 带load，clr等功能的寄存器
// Register Inference
// download from: http://www.fpga.com.cn 

module reginf(d, clk, clr, pre, load, data,
			  q1, q2, q3, q4, q5, q6, q7);

	input d, clk, clr, pre, load, data;
	output q1, q2, q3, q4, q5, q6, q7;
	reg q1, q2, q3, q4, q5, q6, q7;

    // Register with active-high Clock
	always @(posedge clk)
		q1 = d;

    // Register with active-low Clock
	always @(negedge clk)
		q2 = d;

    // Register with active-high Clock & asynchronous Clear
	always @(posedge clk or posedge clr) begin
		if (clr)
			q3 = 0;
		else
			q3 = d;
	end

    // Register with active-low Clock & asynchronous Clear
	always @(negedge clk or negedge clr) begin
		if (!clr)
			q4 = 0;
		else
			q4 = d;
	end

    // Register with active-high Clock & asynchronous Preset
	always @(posedge clk or posedge pre) begin
		if (pre)
			q5 = 1;
		else
			q5 = d;
	end

    // Register with active-high Clock & asynchronous Load
	always @(posedge clk or posedge load) begin
		if (load)
			q6 = data;
		else
			q6 = d;
	end

    // Register with active-high Clock & asynchronous Clear & Preset
	always @(posedge clk or posedge clr or posedge pre) begin
		if (clr)
			q7 = 0;
		else if (pre)
			q7 = 1;
		else
			q7 = d;
	end

endmodule
移位寄存器
//
//
//-----------------------------------------------------------------------------------
// DESCRIPTION   :  Shift register
//                  Type : univ
//                  Width : 4
//                  Shift direction: right/left (right active high)
//
//                  CLK active : high
//                  CLR active : high
//                  CLR type : synchronous
//                  SET active : high
//                  SET type : synchronous
//                  LOAD active : high
//                  CE active : high
//                  SERIAL input : SI
//
// Download from :  http://www.pld.com.cn
//-----------------------------------------------------------------------------------


module shft_reg (CLR , SET , DIR , CE , LOAD , DATA , SI , data_out , CLK );
input CLR , SET , CE , LOAD , DIR , SI , CLK ;
input [3:0] DATA ;
output [3:0] data_out ;



reg [3:0] TEMP;

	always @(posedge CLK )
	begin
		if (CE == 1'b1)
			if (CLR == 1'b1)
				TEMP = {4{1'b0}};
			else if (SET == 1'b1)
				TEMP = {4{1'b1}};
			else if (LOAD == 1'b1)
				TEMP = DATA ;
			else if (DIR == 1'b1)
				TEMP = {SI , TEMP [3:1]};
			else
				TEMP = {TEMP [2:0], SI };
	end

	assign data_out = TEMP;
endmodule

各种类型计数器 
// Efficient Counter Inference
// download from: www.pld.com.cn & www.fpga.com.cn 

module counters (d, clk, clear, ld, enable, up_down,
    	        qa, qb, qc, qd, qe, qf, qg,
 		qh, qi, qj, qk, ql, qm, qn);

   input   [7:0] d;
   input   clk, clear, ld, enable, up_down;
   output  [7:0] qa, qb, qc, qd, qe, qf, qg;
   output  [7:0] qh, qi, qj, qk, ql, qm, qn;

   reg     [7:0] qa, qb, qc, qd, qe, qf, qg;
   reg     [7:0] qh, qi, qj, qk, ql, qm, qn;


   integer direction;

   // An enable counter
   always @(posedge clk) 
   begin
	if (enable)
		qa = qa + 1;
   end


   // A synchronous load counter
   always @(posedge clk) 
   begin
	if (!ld)
		qb = d;
	else
		qb = qb + 1;
   end


   // A synchronous clear counter
   always @(posedge clk)
   begin
	if (!clear)
		qc = 0;
	else
		qc = qc + 1;
   end


   // An up/down counter
   always @(posedge clk) 
   begin
	if (up_down)
		direction = 1;
	else
		direction = -1;
		qd = qd + direction;
   end


   // A synchronous load enable counter
   always @ (posedge clk) 
   begin
	if (!ld)
		qe = d;
	else if (enable)
		qe = qe + 1;
   end


   // An enable up/down counter
   always @(posedge clk) 
   begin
	if (up_down)
		direction = 1;
	else
		direction = -1;
		if (enable)
			qf = qf + direction;
   end


   // A synchronous clear enable counter
   always @(posedge clk) 
   begin
	if (!clear)
		qg = 0;
	else if (enable)
		qg = qg + 1;
   end


   // A synchronous load clear counter
   always @(posedge clk) 
   begin
	if (!clear)
		qh = 0;
	else if (!ld)
		qh = d;
	else
		qh = qh + 1;
   end


   // A synchronous load up/down counter
   always @(posedge clk) 
   begin
	if (up_down)
		direction = 1;
	else
		direction = -1;

	if (!ld)
		qi = d;
	else
		qi = qi + direction;
   end


   // A synchronous load enable up/down counter
   always @(posedge clk) 
   begin
	if (up_down)
		direction = 1;
	else
		direction = -1;

	if (!ld)
		qj = d;
	else if (enable)
		qj = qj + direction;
   end


   // A synchronous clear load enable counter
   always @(posedge clk) 
   begin
	if (!clear)
		qk = 0;
	else if (!ld)
		qk = d;
	else if (enable)
		qk = qk + 1;
   end


   // A synchronous clear up/down counter
   always @(posedge clk) 
   begin
	if (up_down)
		direction = 1;
	else
		direction = -1;

	if (!clear)
		ql = 0;
	else if (enable)
		ql = ql + direction;
   end


   // A synchronous clear enable up/down counter
   always @(posedge clk) 
   begin
	if (up_down)
		direction = 1;
	else
		direction = -1;

	if (!clear)
		qm = 0;
	else if (enable)
		qm = qm + direction;
   end


   // A modulus 200 up counter
   always @(posedge clk) 
   begin
	if (qn == 200)
		qn = 0;
	else
		qn = qn + 1; 
   end

endmodule