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简单实用的FPGA备频程序(verilog)

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2007-04-25 00:14:46     打赏
module dou(clk,a,b);
input clk,a;
output b;
reg b;
reg [31:0] count; //记录输入方波的脉宽
reg [31:0] wide; //计算输出方波的脉宽
reg [31:0] rega;
reg [31:0] regb;
reg [31:0] regc;
reg [31:0] regd;
reg [1:0] state; //状态位
parameter ready=2'b00,high=2'b01,low=2'b10;
initial
begin
count=32'h0000;
wide=32'h0000;
rega=32'h0000;
regb=32'h0000;
state=ready;
end
////////////////////////////////////测量输入脉宽并计算输出脉宽
always @(posedge clk or posedge a)
begin
if(a)
count<=count+1;
else
begin
if(wide==32'h0000)
begin
wide<=(count>>1);
regc<=count;
regd<=count;
end
else if(regd!=regc)
begin
count<=32'h0000;
wide<=32'h0000;
end
else begin
regd<=count;
count<=32'h0000;
end
end
end
////////////////////////////////产生输出方波的状态机
always @(posedge clk)
begin
if(wide==32'h0000)
begin
b<=0;
state<=ready;
end
else
begin
case(state)
ready: begin
rega<=32'h0000;
regb<=32'h0000;
state<=high;
end
high: begin
b<=1;
rega<=rega+1;
if(rega==wide)
state<=low;
else state<=high;
end
low: begin
b<=0;
regb<=regb+1;
if(regb==wide)
state<=ready;
else state<=low;
end
endcase
end
end
endmodule



关键词: 简单     用的     备频     程序     verilog     begin    

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