EEPW论坛

转网友bigoal 问题如下，哪位高手回答下吧！

我编写如下程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dds is
port(frec:in std_logic_vector(23 downto 0);
clk:in std_logic;
wr:in std_logic;
sin_out:out std_logic_vector(7 downto 0)
);
end dds;
architecture beh of dds is
signal phase_adder,frq_reg:std_logic_vector(23 downto 0);
signal rom_address,address:std_logic_vector(7 downto 0);
signal rom_out:std_logic_vector(7 downto 0);
signal s1,s2,a1,a2:std_logic;
component dds_rom
port(add:in std_logic_vector(7 downto 0);
inclock:in std_logic;
q:out std_logic_vector(7 downto 0)
);
end component;
begin
data:dds_rom port map(address,clk,rom_out);
datain:process(clk)
begin
if(clk'event and clk='1') then
if(wr='0') then
frq_reg