EEPW论坛

这是顶层文件，但不知道为什么步进电机就是不转，时序图都是对的！
library ieee;
use ieee.std_logic_1164.all;
entity top is
 port(clk,start,rst,path:in std_logic;
      input:in std_logic_vector(6 downto 0);
      co,ln1,ln2,ln3,ln4:out std_logic;
      cout0,cout1,cout2: out std_logic_vector(6 downto 0));
end top;
architecture behav of top is
  component fr
    port(clk,cp,start,rst,path:in std_logic;
       input:in std_logic_vector(6 downto 0);
       cout0,cout1,cout2: out std_logic_vector(3 downto 0);
       co,ln1,ln2,ln3,ln4:out std_logic);
   end component;
  component cnt1
    port (clk,rst:in std_logic;
        cout:out std_logic);
   end component;
  component cnt2
    port (clk,rst:in std_logic;
        cout:out std_logic);
   end component;
  component decl7s
    port(A:in std_logic_vector(3 downto 0);
         led7s:out std_logic_vector(6 downto 0));
  end component;
 signal a,b,c:std_logic;
 signal d,e,f:std_logic_vector(3 downto 0);
  begin
   u1:fr port map(clk=>b,cp=>a,start=>start,rst=>rst,path=>path,input=>input,co=>co,cout0=>d,cout1=>e,cout2=>f,ln1=>ln1,ln2=>ln2,ln3=>ln3,ln4=>ln4);
   u2:cnt1 port map(clk=>clk,rst=>rst,cout=>a);
   u3:cnt2 port map(clk=>a,rst=>rst,cout=>b);
   u4:decl7s port map(A=>d,led7s=>cout0);
   u5:decl7s port map(A=>e,led7s=>cout1);
   u6:decl7s port map(A=>f,led7s=>cout2);
end behav;