【应用手册】General-Purpose PLLs in Stratix & Stratix GX Devices
Stratix® and Stratix GX devices have highly versatile phase-locked loops
(PLLs) that provide robust clock management and synthesis for on-chip
clock management, external system clock management, and high-speed
I/O interfaces. There are two types of PLLs in each Stratix and Stratix GX
device: enhanced PLLs and fast PLLs. Each device has up to four
enhanced PLLs, which are feature-rich, general-purpose PLLs supporting
advanced capabilities such as external feedback, clock switchover, phase
and delay control, PLL reconfiguration, spread spectrum clocking, and
programmable bandwidth. There are also up to eight fast PLLs per
device, which offer general-purpose clock management with
multiplication and phase shifting as well as high-speed outputs to
manage the high-speed differential I/O interfaces.
The Altera® Quartus® II software enables the PLLs and their features
without requiring any external devices.ch_1_vol_2(Replaces AN 200).pdf
我要赚赏金打赏帖 |
|
|---|---|
| 【S32K3XX】FlexCAN 模块配置使用被打赏¥30元 | |
| 【S32K3XX】FlexCAN RAM 资源分配整理被打赏¥25元 | |
| 【S32K3XX】IPCF 适配核间中断处理被打赏¥21元 | |
| 【S32K3XX】IPCF 核间通讯模块UNMANAGED方式使用被打赏¥29元 | |
| 片外存储Flash使用方法(Arduino IDE环境)被打赏¥22元 | |
| 三分钟快速上手ESP-NOW(ArduinoIDE环境)被打赏¥23元 | |
| 【S32K3XX】LPSPI参数配置说明被打赏¥21元 | |
| 在WT9932C61-TINY上实现超声波测距被打赏¥22元 | |
| 基于WT9932C61-TINY的环境构建及OLED屏驱动测试被打赏¥20元 | |
| 【S32K3XX】Core-to-Core 中断使用被打赏¥21元 | |
我要赚赏金
