这些小活动你都参加了吗?快来围观一下吧!>>
电子产品世界 » 论坛首页 » 嵌入式开发 » FPGA » 【应用手册】AN 608: HST Jitter and BER Estimat

共1条 1/1 1 跳转至

【应用手册】AN 608: HST Jitter and BER Estimator Tool for Stratix IV GX and GT Devices

高工
2012-04-30 19:17:55     打赏
【应用手册】AN 608: HST Jitter and BER Estimator Tool for Stratix IV GX and GT Devices
The high-speed communication link design toolkit (HST) jitter and bit error rate (BER)
estimator tool is a statistical behavior model-based simulation tool that estimates the
jitter and BER performance for high-speed links. You can use the HST jitter and BER
estimator tool for link jitter and BER estimation, optimization, testing, and validation.
This application note describes the technologies and capabilities of the HST jitter and
BER estimator tool.
For an HSIO link, the dominant contributor to system BER is the jitter from all the
subsystems of the link, including the TX, RX, and channel. This application note
describes the theory and methodology that provides answers to the following
questions:
■ What is the relationship between the BER and the jitter from each of the link
subsystems?
■ How to estimate one of the link’s subsystem jitter value if the overall BER and
other subsystems’ jitter values are known?an608.pdf



关键词: 应用     手册     Jitter     Estimator     St    

共1条 1/1 1 跳转至

回复

匿名不能发帖!请先 [ 登陆 注册 ]