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This application note describes the 10 Gigabit Ethernet Physical Coding Sublayer (PCS) reference design for Xilinx Virtex™-II and Virtex-II Pro FPGAs. The PCS connects between a Xilinx RocketPHY™ 10 Gb/s transceiver and the Xilinx LogiCORE™ 10 Gigabit Ethernet Media Access Controller (MAC) core, LogiCORE XAUI core or 10 Gigabit Media Independent Interface (XGMII) Reference Design (XAPP606). This product is not recommended for new designs.

xapp775.pdf