【应用手册】Achieving Timing Closure in Basic (PMA Direct) Functional Mode
This application note describes the method to achieve timing closure for designs that
use transceivers in Basic (PMA Direct) mode in Altera’s Stratix® IV GX or
Stratix IV GT FPGAs. It also describes best practices for the Quartus® II software
version 9.1 SP1 and earlier and best practices for the Quartus II software version
9.1 SP2 and later.
This application note describes techniques for resolving timing violations for paths
between the transceiver and the FPGA core only. You must follow general best
practices for timing closure in FPGA designs to resolve any timing violations that
exist in the FPGA core.an580.pdf