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视频：

视频地址：http://www.tudou.com/v/FlL8Hp4eCxY/&resourceId=109828786_05_11_99&bid=05/v.swf
分频器模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

ENTITY CLKDIV IS
PORT (
CLK :IN STD_LOGIC;
CLK_DIV :OUT STD_LOGIC
);
END ENTITY;

ARCHITECTURE ONE OF CLKDIV IS
SIGNAL COUNT : STD_LOGIC_VECTOR(22 DOWNTO 0);
SIGNAL CLK_DIV_TEMP : STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')
THEN
IF(COUNT>= 2499999)
THEN
COUNT<=(OTHERS =>'0');
CLK_DIV_TEMP<=NOT CLK_DIV_TEMP;
ELSE
COUNT <= COUNT + 1;
END IF;
END IF;
END PROCESS;
CLK_DIV<=CLK_DIV_TEMP;
END ONE;



加减计数器模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY UP_DOWN_CNT8 IS
PORT (
CLK :IN STD_LOGIC;
EN :IN STD_LOGIC;
RESET :IN STD_LOGIC;
DATA :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;

ARCHITECTURE ONE OF UP_DOWN_CNT8 IS
SIGNAL COUNT : STD_LOGIC_VECTOR(8 DOWNTO 0):="000000000";
SIGNAL L_D : STD_LOGIC :='0';
BEGIN
PROCESS(CLK,EN,RESET)
BEGIN
IF(RESET='0')THEN COUNT<="111111111";
ELSIF(EN='0')THEN
IF(CLK'EVENT AND CLK='1')
THEN
IF(COUNT<="11111111" AND COUNT>="00000000")THEN
IF( L_D='0')THEN
COUNT <= COUNT + 1;
END IF;
IF(L_D='1')THEN
COUNT <= COUNT - 1;
END IF;
ELSIF(L_D='0')
THEN L_D<=NOT L_D;
COUNT<="011111111";
ELSE L_D<=NOT L_D;
COUNT<="000000000";
END IF;
END IF;
END IF;

END PROCESS;
DATA<=COUNT(7 DOWNTO 0);
END ONE;

整体设计

哦，这样啊，我昨天，哦不，今天凌晨邮件给你了

顶楼主啊，还是菜鸟，看看各位大侠的东西很有启发呀